Cache bypass system with simultaneous initial transfer of target data to

Abstract

A data processor which accesses a memory system only by a block transfer mode for transferring multiple data from the memory system when a cache misses a CPU read-access request for a single data. The data of the address designated by the CPU is read simultaneously into the CPU and cache in parallel from the memory system. After the CPU completes this read-access, the cache is then adapted to continue to read the rest of the multiple data transferred in the block transfer mode. During this time, the CPU does not newly assert an address signal, a bus control signal, and the like but continues to execute its internal processing, such as pipeline processing.