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For the Inventor, By the Inventor

Hyogo, Japan

Hirokazu Ueda

USPTO Granted Patents = 8 

Average Co-Inventor Count = 1.3

ph-index = 5

Forward Citations = 45(Granted Patents)


Location History:

  • Nishiwaki, JP (2005 - 2006)
  • Hyogo, JP (2002 - 2007)
  • Kobe, JP (2007 - 2008)

Company Filing History:

goldMedal7 out of 38,023 
 
Micron Technology Incorporated
 patents
silverMedal2 out of 2 
 
Kmt Semiconductor, Ltd
 patents
where one patent can have more than one assignee

Years Active: 2002-2008

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8 patents (USPTO):Explore Patents
1. 7366051 - Word line driver circuitry and methods for using the same (2008-04-29),
2. 7269091 - Word line driver circuitry and methods for using the same (2007-09-11),
3. 7268402 - Memory cell with trench-isolated transistor including first and second isolation trenches (2007-09-11),
4. 7116596 - Method of apparatus for enhanced sensing of low voltage memory (2006-10-03),
5. 6894354 - Trench isolated transistors, trench isolation structures, memory cells, and DRAMs (2005-05-17),
6. 6873559 - Method and apparatus for enhanced sensing of low voltage memory (2005-03-29),
7. 6830977 - METHODS OF FORMING AN ISOLATION TRENCH IN A SEMICONDUCTOR, METHODS OF FORMING AN ISOLATION TRENCH IN A SURFACE OF A SILICON WAFER, METHODS OF FORMING AN ISOLATION TRENCH-ISOLATED TRANSISTOR, TRENCH-ISOLATED TRANSISTOR, TRENCH ISOLATION STRUCTURES FORMED IN A SEMICONDUCTOR, MEMORY CELLS AND DRAMS (2004-12-14),
8. 6387735 - Method for manufacturing field effect transistor capable of successfully controlling transistor characteristics relating to the short-channel effect (2002-05-14),

Title: Hirokazu Ueda: Innovator in Semiconductor Technology

Introduction

Hirokazu Ueda is a prominent inventor based in Hyogo, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 8 patents. His innovative work has advanced the design and functionality of memory cell circuitry.

Latest Patents

Ueda's latest patents include groundbreaking inventions such as "Word line driver circuitry and methods for using the same." This patent describes a dual transistor topology that selectively charges and discharges word lines. The design utilizes a signal, DOUT, and its time-delayed complement, DOUT_BAR, to minimize leakage current during operation. Another notable patent is for a "Memory cell with trench-isolated transistor including first and second isolation trenches." This invention features a unique isolation trench design that enhances the performance of semiconductor devices.

Career Highlights

Throughout his career, Hirokazu Ueda has worked with leading companies in the semiconductor industry, including Micron Technology Incorporated and KMT Semiconductor, Ltd. His experience in these organizations has allowed him to refine his skills and contribute to significant advancements in technology.

Collaborations

Ueda has collaborated with notable colleagues such as Keiji Jono and Hiroyuki Watanabe. These partnerships have fostered innovation and have been instrumental in the development of his patented technologies.

Conclusion

Hirokazu Ueda's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the field. His work continues to influence advancements in memory cell design and functionality.

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