Hiroaki Kobayashi

Title: Hiroaki Kobayashi and IC Fault Location Tracing

Introduction

Hiroaki Kobayashi is an inventor associated with Kumagaya, Japan, and Advantest Corporation. His patent work includes an apparatus and method designed to help users locate faults in integrated circuits, even without detailed knowledge of the device under test’s design.

Latest Patents

Kobayashi’s listed patent is “IC Fault Location Tracing Apparatus and Method.” The invention aims to make identifying an IC fault location faster and more accessible. It uses a control device to direct visual-field data to a charged-particle-ray tester and capture images of electrical-potential contrast.

The control device recognizes suspected fault-related layout patterns and their output gates, identifies input-net polygons associated with those gates, and determines the next visual field for tracing the fault. It also displays and sends the next layout or visual-field data to the tester. A memory stores information linking net layouts and device layouts. Kobayashi is credited with 1 patent.

Career Highlights

Kobayashi’s listed invention addresses a practical challenge in semiconductor testing: locating faults efficiently without requiring users to understand the DUT’s design in depth. His work connects layout recognition, image capture, and visual-field selection in a guided tracing process.

Collaborations

Hironobu Niijima is identified as Kobayashi’s coworker. The available information does not specify their roles in developing the patent.

Conclusion

Hiroaki Kobayashi’s patent describes a guided approach to IC fault tracing that combines layout recognition, charged-particle imaging, and stored design information to help users identify fault locations more efficiently.