Adv Antest Corporation

Hiroaki Kobayashi

Hironobu Niijima

The present invention is to provide an IC fault location tracing apparatus with which a user having any knowledge of the DUT design is easily able to identify the IC fault location in a short period of time. The IC fault location tracing apparatus of the present invention includes a control device instructing visual field data to the charged particle ray tester and capturing different images of said electric potential contrast images from the charged particle ray tester, wherein said control device further includes: a fault-suspected layout pattern/net recognition means; a n output gate recognition means for fault-suspected layout patterns; an input net polygon recognition means corresponding to input net of the output gate of the fault-suspected layout pattern; a visual field determination means determining next visual field data for tracing fault location; a layout (visual field) display means instructing next layout (visual field) data to the charged particle ray tester; a memory device storing net layout corresponding information and device-layout corresponding information.

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Kumagaya, Japan

Hiroaki Kobayashi