Kamakura, Japan

Hidefumi Kushibe

This inventor holds 8 USPTO granted patents and 2 published patent applications. Top assignees: Toshiba Memory Corporation, Kabushiki Kaisha Toshiba. Active years: 1999-2021.

USPTO Granted Patents = 8 

% Patents Active = 75.0

Average Co-Inventor Count = 1.7

ph-index = 2

Forward Citations = 14(Granted Patents)


Location History:

  • Kamakura, JP (1999 - 2018)
  • Kamakura Kanagawa, JP (2021)

Company Filing History:


Years Active: 1999-2021

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8 patents (USPTO):Explore Patents

Title: The Innovations of Hidefumi Kushibe

Introduction

Hidefumi Kushibe is a prominent inventor based in Kamakura, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 8 patents. His work focuses on enhancing the performance and efficiency of semiconductor devices and memory systems.

Latest Patents

Kushibe's latest patents include a semiconductor device and memory system. In one embodiment, a first differential amplifier circuit of a semiconductor device is described, where a first transistor receives an input signal at the gate. A second transistor forms a differential pair with the first transistor, receiving a reference signal at its gate. Additionally, a third transistor is connected in series with the first transistor, while a fourth transistor is connected in series with the second transistor. A fifth transistor is disposed on the output side, forming a first current mirror circuit with the fourth transistor. Furthermore, a sixth transistor is connected to the drain of the second transistor in parallel with the fourth transistor, forming a second current mirror circuit with the fifth transistor. A first discharge circuit is connected to the source of the sixth transistor.

Another notable patent is a semiconductor integrated circuit with a regulator circuit provided between an input terminal and an output terminal. This circuit includes an output transistor, an error amplifier, and a control circuit. The output transistor connects between a first node on the input terminal side and a second node on the output terminal side. The error amplifier has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal connects to a third node between the second node and a standard potential, while the inverting input terminal connects to a reference voltage. The output terminal connects to the gate of the output transistor, and the control circuit adjusts the responsiveness of the error amplifier at startup to be slower than during steady operation.

Career Highlights

Kushibe has worked with notable companies in the semiconductor industry, including Toshiba Memory Corporation and Kabushiki Kaisha Toshiba. His experience in these organizations has allowed him to develop innovative solutions that address the challenges faced in semiconductor technology.

Collaborations

Throughout his career, Kushibe has collaborated with talented individuals such as Hiroyuki Ideno and Masashi Nakata. These partnerships have contributed to the advancement of his inventions and the overall progress in the field.

Conclusion

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Profile summary based on public USPTO records.
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