Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Hidefumi Kushibe

Hiroyuki Ideno

Masashi Nakata

Masayuki Usuda

Yohei Yasuda

Toshihiro Yagi

According to one embodiment, in a first differential amplifier circuit of a semiconductor device, a first transistor receives an input signal at the gate. A second transistor forms a differential pair with the first transistor. The second transistor receives a reference signal at the gate. A third transistor is connected in series with the first transistor. A fourth transistor is connected in series with the second transistor. A fifth transistor is disposed on the output side. The fifth transistor forms a first current mirror circuit with the fourth transistor. A sixth transistor is connected to the drain of the second transistor in parallel with the fourth transistor. The sixth transistor forms a second current mirror circuit with the fifth transistor. A first discharge circuit is connected to the source of the sixth transistor.

Semiconductor device and memory system

According to one embodiment, there is provided a semiconductor integrated circuit including an output transistor, an error amplifier, and a control circuit. The output transistor is connected between a first node on an input terminal side and a second node on an output terminal side. The error amplifier has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is connected to a third node between the second node and a standard potential. The inverting input terminal is connected to a reference voltage. The output terminal is connected to the gate of the output transistor. The control circuit makes responsiveness of the error amplifier at startup slower than responsiveness of the error amplifier at steady operation.

Semiconductor integrated circuit with a regulator circuit provided between an input terminal and an output terminal thereof

According to one embodiment, in a semiconductor integrated circuit, a first input terminal of an error amplifier is electrically connected to a third node between a second node and a reference potential. A second input terminal of the error amplifier is electrically connected to a reference voltage. An output terminal of the error amplifier is electrically connected to a gate of an output transistor. A first input terminal of a comparator is electrically connected to a fourth node between the second node and the reference potential. A second input terminal of the comparator is electrically connected to the reference voltage. One end of a coupling capacitance is electrically connected to an output terminal of the comparator. A gate of an auxiliary transistor is electrically connected to the other end of the coupling capacitance. A drain of the auxiliary transistor is electrically connected to the second node.

Semiconductor integrated circuit

According to one embodiment, there is provided a semiconductor device including an input terminal, an output terminal, an oscillation circuit, an adjuster circuit, a driver circuit, and a detector circuit. The input terminal receives a first clock. The oscillation circuit generates an internal clock. The adjuster circuit corrects a duty ratio of a clock. The driver circuit receives the clock from the adjuster circuit and supplies a third clock to the output terminal. The detector circuit detects that a duty ratio of a clock according to the third clock deviates from a duty ratio of a second clock according to the internal clock. The adjuster circuit adjusts a correction amount in tune with the second clock, and corrects a duty ratio of the first clock with the adjusted correction amount according to a detection result of the detector circuit.

Semiconductor device

According to one embodiment, an integrated circuit is formed on a semiconductor chip, a regulator supplies power to the integrated circuit via the power-supply wire, a first resistor is connected between the first pad electrode and the power-supply wire on the semiconductor chip, and a second resistor is connected between the second pad electrode and the power-supply wire on the semiconductor chip and has a resistance smaller than that of the first resistor.

According to one embodiment, a regulator is provided which comprises a reference voltage generating circuit that generates a reference voltage, a first voltage dividing circuit that divides a regulator output in voltage, an error amplifier that compares a first divided voltage obtained by dividing the regulator output and the reference voltage, and an output transistor that generates the regulator output based on the output of the error amplifier. The reference voltage generating circuit comprises a diode-connected first transistor. The reference voltage is generated based on a diode voltage generated by the first transistor.

Regulator and semiconductor integrated circuit

There is disclosed a phase locked loop circuit comprising a phase frequency comparator configured to output an up/down signal indicating a phase difference and a frequency difference between a reference signal and a frequency divided signal, a charge pump configured to output a current signal in accordance with said up/down signal, an oscillator configured to output an oscillation signal of a frequency in accordance with said current signal, frequency dividing parts configured to divide the frequency of said oscillation signal and generating said frequency divided signal, phase frequency judging parts configured to judge whether or not the phase difference and the frequency difference between said reference signal and said frequency divided signal exceed a predetermined reference value, and changeover parts configured to switch a value of a current flowing through said charge pump depending upon whether or not the phase difference and the frequency difference between said reference signal and said frequency divided signal exceed said reference value.

Phase locked loop circuit

There are provided a start circuit for a constant current circuit, a constant current circuit including the start circuit, and an operational amplifier including the constant current circuit. When an output stop signal PD changes from an inactivation mode to an activation mode, changes of transistors MN3 and MP6 to their off states are delayed for a moment by a delay circuit DL or a switch SW1 to temporarily lower the bias node and to reliably start the circuit. Therefore, the circuit does not need a large capacitor and prevents entry of noise through the capacitor.

Growing community of inventors

Kamakura, Japan

Hidefumi Kushibe