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For the Inventor, By the Inventor

Santa Clara, CA, United States of America

Harshvardhan P Sharangpani

This inventor holds 36 USPTO granted patents and 3 EPO patents, primarily in Programmable Processors. Top assignees: Intel Corporation, Idea Corporation, Cisco Technology, Inc.. Active years: 1994-2008.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Harshvardhan P Sharangpani. Retrieved from https://idiyas.com/inventor/harshvardhan-p-sharangpani

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 36

% Patents Active = 91.7


Average Co-Inventor Count = 2.0

ph-index = 21

Forward Citations = 1,329(Granted Patents)


Company Filing History:

goldMedal28 out of 56,365 
 
Intel Corporation
 patents
silverMedal3 out of 17 
 
Idea Corporation
 patents
bronzeMedal2 out of 21,399 
 
Cisco Technology, Inc.
 patents
4. 1 out of 133 
 
Cisco Systems Inc.
 patents
5. 1 out of 34 
 
Institute for the Development of Emerging Architectures, L.l.c.
 patents
6. 1 out of 834,570 
Other
 patents

Years Active: 1994-2008

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Areas of Expertise:
Programmable Processors
Contextual Searches
State Machines
Execution Hardware
Branch Prediction
Instruction Processing
Data Processing
Floating Point Operations
Dynamic Scheduling
Hazard Detection
Register Files
Performance Optimization
36 patents (USPTO):Explore Patents
1. 7464254 - Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data (2008-12-09),
2. 7451143 - Programmable rule processing apparatus for conducting high speed contextual searches and characterizations of patterns in data (2008-11-11),
3. 7119577 - Method and apparatus for efficient implementation and evaluation of state machines and programmable finite state automata (2006-10-10),
4. 6629232 - Copied register files for data processors having many execution units (2003-09-30),
5. 6625693 - Fast exception processing (2003-09-23),
6. 6611910 - Method for processing branch operations (2003-08-26),
7. 6591359 - Speculative renaming of data-processor registers (2003-07-08),
8. 6553488 - Method and apparatus for branch prediction using first and second level branch prediction tables (2003-04-22),
9. 6401195 - Method and apparatus for replacing data in an operand latch of a pipeline stage in a processor during a stall (2002-06-04),
10. 6378063 - Method and apparatus for efficiently routing dependent instructions to clustered execution units (2002-04-23),
11. 6272520 - Method for detecting thread switch events (2001-08-07),
12. 6240510 - System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions (2001-05-29),
13. 6237077 - Instruction template for efficient processing clustered branch instructions (2001-05-22),
14. 6233690 - Mechanism for saving power on long latency stalls (2001-05-15),
15. 6178498 - Storing predicted branch target address in different storage according to importance hint in branch prediction instruction (2001-01-23),

Title: The Innovative Mind of Harshvardhan P Sharangpani

Introduction

Harshvardhan P Sharangpani, a renowned inventor based in Santa Clara, CA, has made significant contributions to the field of technology with an impressive portfolio of 36 patents. His work primarily focuses on advanced processing technologies, reflecting his commitment to innovation and excellence.

Latest Patents

One of his latest patents is a programmable processor apparatus that integrates dedicated search registers and state machine registers. This invention features associated execution hardware designed to facilitate the rapid application of rulesets to data. The rule processor outlined in this patent comprises a general-purpose register file, an instruction sequencer, a decoder, and a state machine unit, allowing for efficient evaluation of state machines in response to executed instructions. Additionally, he developed a programmable rule processing apparatus for conducting high-speed contextual searches and characterizations of patterns in data. This method involves a rule processor that utilizes a plurality of input payload search registers and a search execution engine, enabling parallel pattern matching based on specified rules.

Career Highlights

Throughout his career, Harshvardhan has worked with prestigious companies, including Intel Corporation and Idea Corporation. His work in these organizations has focused on developing cutting-edge technologies that enhance data processing capabilities and improve efficiency in various applications. His extensive patent portfolio showcases his innovative approach and expertise in the field.

Collaborations

During his professional journey, Harshvardhan has collaborated with notable individuals such as Hans J Mulder and Kent G Fielden. These collaborations have further enriched his work and contributed to the success of various innovative projects.

Conclusion

Harshvardhan P Sharangpani stands out as a prominent figure in the world of technology, with a clear passion for innovation. His extensive contributions through patents and collaborations reflect his dedication to pushing the boundaries of what is possible in the realm of data processing and contextual search technologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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