The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2001
Filed:
Sep. 17, 1998
Applicant:
Inventors:
Lynn Choi, Irvine, CA (US);
Harshvardhan Sharangpani, Santa Clara, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 ;
U.S. Cl.
CPC ...
G06F 1/32 ;
Abstract
A method for gating a clock signal to an execution unit on long latency memory stalls monitors a stall signal, a scoreboard (data) hazard signal, a resource hazard signal, and a data return signal. The clock signal is decoupled from the execution unit when the stall and data hazard signals are asserted for a selected interval and the data return and resource hazard signals are not asserted for a selected interval.
Choi, Lynn. (2001). Mechanism for saving power on long latency stalls (U.S. Patent No. 6233690). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6233690
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile