San Jose, CA, United States of America

Harsh Dev Sharma


Average Co-Inventor Count = 6.0

ph-index = 3

Forward Citations = 51(Granted Patents)


Location History:

  • Santa Jose, CA (US) (2009)
  • San Jose, CA (US) (2010 - 2011)

Company Filing History:


Years Active: 2009-2011

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3 patents (USPTO):Explore Patents

Title: The Innovative Mind of Harsh Dev Sharma in Integrated Circuit Design

Introduction

Harsh Dev Sharma, an accomplished inventor based in San Jose, CA, has made significant contributions to the field of integrated circuit design. With a total of three patents to his name, Sharma continues to push the boundaries of innovation in electronic circuit design, demonstrating a passion for creating more efficient and effective systems.

Latest Patents

One of Harsh’s most notable patents is focused on the visual yield analysis of integrated circuit layouts. This invention introduces innovative systems and methods aimed at optimizing layouts based on yield analysis. The method entails generating an integrated circuit layout that includes multiple layers of wire interconnect and via contact layers, which link net segments. Additionally, it performs a yield analysis of these net segments and visualizes the results using varying levels of opacity to clearly communicate yield scores.

Another remarkable patent involves a graphical user interface for prototyping early instance density. This invention allows designers to present electronic circuit design information effectively. Harsh's method determines the arrangement of at least two gates within an electronic circuit and calculates the distance between them. The visual indicator is then displayed, reflecting the relative distances using color, brightness, hue, or pattern darkness, facilitating an intuitive understanding of circuit layout dynamics.

Career Highlights

Harsh Dev Sharma is a vital part of Cadence Design Systems, Inc., a leading company in electronic design automation. His contributions to the field are well-recognized, as he consistently applies his innovative thinking to solve complex design challenges. His experience at Cadence further empowers him to explore new realms of possibilities within integrated circuit design.

Collaborations

Throughout his career, Harsh has collaborated with talented professionals such as Rajeev Srivastava and Bharat Bhushan. These partnerships have undoubtedly enriched his work, fostering an environment of creativity and shared expertise in the innovative processes involved in electronic design.

Conclusion

Harsh Dev Sharma exemplifies the spirit of innovation in the field of integrated circuit design. With his impressive patent portfolio and dedication to advancing technology, he remains a driving force in the development of efficient design methodologies. His work not only enhances productivity for engineers and designers but also sets a precedent for future advancements in electronic circuit technology.

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