The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 2011
Filed:
Nov. 28, 2006
Harsh Dev Sharma, San Jose, CA (US);
Rajeev Srivastava, San Jose, CA (US);
Srinivas R. Kommoori, Milpitas, CA (US);
Bharat Bhushan, Santa Clara, CA (US);
Mithunjoy Parui, Mountain View, CA (US);
Albert Lee, Livermore, CA (US);
Harsh Dev Sharma, San Jose, CA (US);
Rajeev Srivastava, San Jose, CA (US);
Srinivas R. Kommoori, Milpitas, CA (US);
Bharat Bhushan, Santa Clara, CA (US);
Mithunjoy Parui, Mountain View, CA (US);
Albert Lee, Livermore, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Systems and methods to optimize a layout based on the yield analysis is disclosed. The method includes generating an integrated circuit layout having two or more layers of wire interconnect to form net segments and having one or more via contact layers to couple net segments in the wire interconnect together. The method further includes performing a yield analysis of the net segments in the integrated circuit layout and displaying the net segments with a visual depiction of the yield analysis using multiple levels of opacity to reflect yield scores of the net segments in the integrated circuit layout.