The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2009
Filed:
Jan. 31, 2007
Harsh Dev Sharma, Santa Jose, CA (US);
Rajeev Srivastava, Cupertino, CA (US);
Srivinas R. Kommoori, Milpitas, CA (US);
Bharat Bhushan, Santa Clara, CA (US);
Mithunjoy Parui, Mountain View, CA (US);
Albert Lee, Livermore, CA (US);
Harsh Dev Sharma, Santa Jose, CA (US);
Rajeev Srivastava, Cupertino, CA (US);
Srivinas R. Kommoori, Milpitas, CA (US);
Bharat Bhushan, Santa Clara, CA (US);
Mithunjoy Parui, Mountain View, CA (US);
Albert Lee, Livermore, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Disclosed are methods, systems and apparatus for automatically placing decoupling capacitors in an integrated circuit to compensate for voltage drops that might otherwise occur in a power grid. In one embodiment of the invention, the method includes generating one or more regions of the integrated circuit design, with each region having one or more cells, determining an amount of decoupling capacitance required in each region of the integrated circuit design by analyzing each cell in the region, and adding sufficient decoupling capacitor cells to the region to compensate for the potential voltage drop.