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For the Inventor, By the Inventor

Allen, TX, United States of America

Harish V Gadamsetty

This inventor holds 6 USPTO granted patents. Top assignee: Micron Technology Incorporated. Active years: 2022-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Harish V Gadamsetty. Retrieved from https://idiyas.com/inventor/harish-v-gadamsetty

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 6

% Patents Active = 100.0

Average Co-Inventor Count = 1.6

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:

goldMedal6 out of 39,176 
 
Micron Technology Incorporated
 patents

Years Active: 2022-2024

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6 patents (USPTO):Explore Patents
1. 12094520 - Memory device layout with intersecting region between sub-wordline and sense amplifier (2024-09-17),
2. 11942171 - Concurrent compensation in a memory system (2024-03-26),
3. 11837316 - Apparatuses and methods to mask write operations (2023-12-05),
4. 11670356 - Apparatuses and methods for refresh address masking (2023-06-06),
5. 11551779 - Global redundant column select implementation for boundary faults in a memory device (2023-01-10),
6. 11232830 - Auto-precharge for a memory bank stack (2022-01-25),

Title: Harish V Gadamsetty: Innovator in Memory Device Technology

Introduction

Harish V Gadamsetty is a prominent inventor based in Allen, TX (US). He has made significant contributions to the field of memory device technology, holding a total of 6 patents. His innovative work has advanced the capabilities of memory systems, making them more efficient and reliable.

Latest Patents

One of his latest patents is titled "Memory device layout with intersecting region between sub-wordline and sense amplifier." This invention includes a memory partition that comprises a memory element coupled to a wordline, a sense amplifier region, and a minigap region at the intersection of the sub-wordline and sense amplifier regions. The minigap features a continuous layout of transistors that enhances the performance of the memory device.

Another notable patent is "Concurrent compensation in a memory system." This method allows for concurrent compensation in a memory array by decoding a prime row address and providing a redundant section signal when a defective prime row address is detected. This innovation initiates threshold voltage compensation operations on sensing circuitry, improving the overall functionality of memory systems.

Career Highlights

Harish V Gadamsetty is currently employed at Micron Technology Incorporated, where he continues to develop cutting-edge memory technologies. His work has been instrumental in enhancing the performance and reliability of memory devices used in various applications.

Collaborations

Throughout his career, Harish has collaborated with notable colleagues, including Kallol Mazumder and John A Winegard. These collaborations have contributed to the successful development of innovative memory solutions.

Conclusion

Harish V Gadamsetty is a distinguished inventor whose contributions to memory device technology have made a significant impact in the field. His innovative patents and ongoing work at Micron Technology Incorporated continue to shape the future of memory systems.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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