Micron Technology Incorporated

Harish V Gadamsetty

Michael Amiel Shore

Scott Eugene Smith

Kallol Mazumder

Gary L Howe

Yoshinori Fujiwara

Jason M Johnson

Dennis G Montierth

John A Winegard

A memory device, includes a memory partition. The memory partition includes a memory region comprising a memory element coupled to a wordline of the memory region, a sense amplifier region comprising a sense amplifier coupled to the memory element to sense a data state of the memory element, a sub-wordline region coupled to the wordline of the memory region, and a minigap region disposed at the intersection of the sub-wordline region and the sense amplifier region. The minigap includes a first plurality of transistors having a continuous layout in at least one direction across the minigap region with a second plurality of transistors of the sense amplifier region.

Memory device layout with intersecting region between sub-wordline and sense amplifier

An example method may be used to perform concurrent compensation in a memory array. The example method may include decoding a prime row address corresponding to a respective prime memory cell row of a first row section of a memory array mat to provide a prime section signal, and in response to a determination that the prime row address matches a defective prime row address, providing a redundant section signal corresponding to a respective redundant memory cell row of a second row section of the memory array mat. In response to the prime section signal, initiating a first threshold voltage compensation operation on first sensing circuitry coupled to the first row section; and in response to the redundant section signal indicating a defective prime row, initiating a second threshold voltage compensation operation on second sensing circuitry coupled to the second row section concurrent with the first threshold voltage compensation operation.

Concurrent compensation in a memory system

An exemplary semiconductor device includes circuitry to implement data mask operations by sending bit-specific, write enable signals (WREN) to control connection of a main or global data line to local data lines during a write operation. For example, a plurality of even sense amplifier stripes each receive a first set of WREN signals to control a corresponding passgate responsible for coupling one global data line to one local data line and a plurality of odd sense amplifier stripes each receive a second set of WREN signals to control a corresponding passgate responsible for coupling one global data line to one local data line.

Apparatuses and methods to mask write operations

Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).

Apparatuses and methods for refresh address masking

An electronic device includes memory banks and repair circuitry configured to remap data from the memory banks to repair memory elements of the memory banks when a failure occurs. The repair circuitry includes a logic gate configured to receive an output from a memory bank of the memory banks, receive a failure signal indicating whether a corresponding memory element has failed, and transmit the output with a value of the output is based at least in part on the failure signal. The repair circuitry also includes error correction circuitry configured to receive the output via the logic gate and a multiplexer configured to receive the output from the memory bank, receive a repair value, and selectively output the output or the repair value from the repair circuitry as an output of the repair circuitry.

Global redundant column select implementation for boundary faults in a memory device

Devices and methods include a command interface configured to receive commands, such as a write with an automatic precharge. A bank-specific decoder decodes the write with an automatic precharge command for a corresponding memory bank and outputs a write auto-precharge (WrAP) signal. This WrAP signal has not been adjusted for a write recovery time for the memory bank. Accordingly, bank processing circuitry in a bank receiving the WrAP signal uses the WrAP to cause its internal lockout circuitry to apply a tWR lockout based at least in part on a mode register setting and on the WrAP signal indicating receipt of the write with an automatic precharge command.

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Allen, TX, United States of America

Harish V Gadamsetty