Bengaluru, India

Harish Mundrathi

This inventor holds 1 USPTO granted patent. Top assignee: Marvell Asia Pte., Ltd.. Active years: 2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Harish Mundrathi. Retrieved from https://idiyas.com/inventor/harish-mundrathi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1


Company Filing History:


Years Active: 2025

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1 patent (USPTO):Explore Patents

Title: Harish Mundrathi: Innovator in Integrated Circuit Testing

Introduction

Harish Mundrathi is a notable inventor based in Bengaluru, India. He has made significant contributions to the field of integrated circuit testing, particularly in power reduction techniques. His innovative approach has led to the development of a patented method that enhances the efficiency of testing integrated circuits.

Latest Patents

Harish Mundrathi holds a patent for a method titled "Clock gating for power reduction during testing." This invention addresses the challenge of power consumption in integrated circuit devices that include components of different types. The method involves gating off the clock signal to prevent unnecessary power consumption by components that are not active during testing. By applying test inputs to the active components while preventing clock signals from reaching the inactive ones, the method significantly reduces power usage.

Career Highlights

Harish is currently employed at Marvell Asia Pte., Ltd., where he continues to work on innovative solutions in the field of integrated circuits. His expertise and dedication to advancing technology have made him a valuable asset to his team and the industry.

Collaborations

Some of Harish's coworkers include Sreekanth G Pai and Harry I Linzer. Their collaboration fosters a creative environment that encourages innovation and the development of cutting-edge technologies.

Conclusion

Harish Mundrathi's contributions to integrated circuit testing through his patented method exemplify the importance of innovation in technology. His work not only enhances testing efficiency but also contributes to the broader field of electronics.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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