Karnataka, India

Gurucharapathy Karthikeyan

This inventor holds 1 USPTO granted patent. Top assignee: Intel Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Gurucharapathy Karthikeyan. Retrieved from https://idiyas.com/inventor/gurucharapathy-karthikeyan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Gurucharapathy Karthikeyan: Inventor in Semiconductor Interconnect Technology.

Introduction

Gurucharapathy Karthikeyan is an inventor associated with Intel Corporation and based in Karnataka, India. His patent work addresses communication between chiplets, the specialized components that can be integrated within a semiconductor package.

Latest Patents

The provided information identifies one patent associated with Karthikeyan: “Inter-chiplet routing of transactions across multi-heterogeneous chiplets using hierarchical addressing.” The invention describes a system in which messages carry destination identifiers with separate portions for identifying a destination chiplet and an agent on that chiplet. A fabric adapter can direct a message to a die-to-die bridge when its destination identifier specifies another chiplet, enabling transactions to be routed across heterogeneous chiplets.

Career Highlights

Karthikeyan’s listed patent reflects work on hierarchical addressing and inter-chiplet communication. The disclosed approach combines agents, fabric adapters, a routing fabric, and a die-to-die bridge to support message delivery between chiplets.

Collaborations

Karthikeyan is associated with Intel Corporation. Ramadass Nagarajan is identified as a coworker; the information provided does not specify their particular collaboration on this patent.

Conclusion

Gurucharapathy Karthikeyan’s listed invention focuses on routing transactions across heterogeneous chiplets, contributing to the broader development of semiconductor interconnect technologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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