Suzhou, China

Geng Zhong


Average Co-Inventor Count = 3.3

ph-index = 1

Forward Citations = 4(Granted Patents)


Location History:

  • Suzhou, CN (2014 - 2015)
  • Austin, TX (US) (2016)

Company Filing History:


Years Active: 2014-2016

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3 patents (USPTO):Explore Patents

Title: Geng Zhong: Innovator in Semiconductor Technology

Introduction

Geng Zhong is a prominent inventor based in Suzhou, China. He has made significant contributions to the field of semiconductor technology, holding a total of 3 patents. His work focuses on improving the performance and reliability of integrated circuits.

Latest Patents

One of Geng Zhong's latest patents is titled "Clock signal alignment for system-in-package (SIP) devices." This patent describes a method that involves receiving a delay value associated with interconnect delay and adjusting a local clock signal accordingly. The method ensures that the master clock signal generated is aligned with the source clock signal from the host semiconductor device. Another notable patent is the "Method of validating timing issues in gate-level simulation." This invention provides a systematic approach to identifying and reporting timing violations in integrated circuit designs, enhancing the accuracy of gate-level simulations.

Career Highlights

Geng Zhong is currently employed at Freescale Semiconductor, Inc., where he applies his expertise in semiconductor design and validation. His innovative approaches have contributed to advancements in the industry, making him a valuable asset to his company.

Collaborations

Geng Zhong has collaborated with notable colleagues, including Chao Liang and Gary L. Miller. Their combined efforts in semiconductor research and development have led to significant technological advancements.

Conclusion

Geng Zhong's contributions to semiconductor technology through his patents and work at Freescale Semiconductor, Inc. highlight his role as an influential inventor in the field. His innovative methods continue to shape the future of integrated circuit design and validation.

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