Freescale Semiconductor,inc.

Geng Zhong

Chao Liang

Gary L Miller

James G Gay

Cheng Wang

Jian Zhou

Gilford E Lubbers

A method embodiment of the present disclosure includes receiving a delay value associated with an interconnect delay that is measured across interconnect circuitry communicatively coupling a host semiconductor device with a semiconductor device. The method also includes delaying a local clock signal by an amount of delay indicated by the delay value to produce a delayed local clock signal. The method also includes receiving a delayed source clock signal, where the delayed source clock signal is received from the host semiconductor device via the interconnect circuitry. The method also includes outputting a master clock signal based on a comparison of the delayed source clock signal and the delayed local clock signal, where the master clock signal is utilized to generate one or more aligned clock signals on the semiconductor device that are aligned with a source clock signal generated on the host semiconductor device.

Clock signal alignment for system-in-package (SIP) devices

A method of validating timing issues in a gate-level simulation (GLS) of an integrated circuit design including multiple cells includes running a simulation routine of a behavioral model of the design and obtaining a first simulation result. If there is a possible timing violation at a cell corresponding to a forcing indeterminate value, the simulated output of the cell is forced to a first value and a second simulation result obtained. If this result is negative, a report of apparent timing violations at the cell is generated. If the second simulation result is positive, the output of the cell is then forced to a second value and a third simulation result is obtained. If this result is negative, a report of apparent timing violations at the cell is generated but, if it is positive, a report of no apparent timing violation is generated.

Method of validating timing issues in gate-level simulation

A method for producing a verified design of a digital to analog converter (DAC) starts with providing an HDL representation of the DAC. Numerical values of the analog output signal as a function of the representation of the DAC for a range of numerical values of the digital input signal are simulated with a simulator. A model is used for converting the simulated numerical values of the analog output signal to numerical values of an equivalent model signal in the same digital format as the input signal. A comparator compares the numerical values of the input signal and the model signal and determines differences greater than a defined tolerance.

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Suzhou, China

Geng Zhong