The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 21, 2016
Filed:
May. 22, 2015
Freescale Semiconductor, Inc., Austin, TX (US);
Gary L. Miller, Austin, TX (US);
James G. Gay, Pflugerville, TX (US);
Gilford E. Lubbers, Dripping Springs, TX (US);
Geng Zhong, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method embodiment of the present disclosure includes receiving a delay value associated with an interconnect delay that is measured across interconnect circuitry communicatively coupling a host semiconductor device with a semiconductor device. The method also includes delaying a local clock signal by an amount of delay indicated by the delay value to produce a delayed local clock signal. The method also includes receiving a delayed source clock signal, where the delayed source clock signal is received from the host semiconductor device via the interconnect circuitry. The method also includes outputting a master clock signal based on a comparison of the delayed source clock signal and the delayed local clock signal, where the master clock signal is utilized to generate one or more aligned clock signals on the semiconductor device that are aligned with a source clock signal generated on the host semiconductor device.