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For the Inventor, By the Inventor

Fort Collins, CO, United States of America

Eric R DeLano

This inventor holds 14 USPTO granted patents. Top assignees: Hewlett-Packard Company, Hewlett-Packard Development Company, L.p., Intel Corporation. Active years: 1995-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Eric R DeLano. Retrieved from https://idiyas.com/inventor/eric-r-delano-czabf3an

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 14

% Patents Active = 71.4

Average Co-Inventor Count = 2.1

ph-index = 8

Forward Citations = 298(Granted Patents)


Location History:

  • Ft Collins, CO (US) (2002)
  • Fort Collins, CO (US) (1995 - 2020)

Company Filing History:

goldMedal6 out of 9,639 
 
Hewlett-Packard Company
 patents
silverMedal6 out of 27,687 
 
Hewlett-Packard Development Company, L.p.
 patents
bronzeMedal2 out of 56,365 
 
Intel Corporation
 patents

Years Active: 1995-2020

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14 patents (USPTO):Explore Patents
1. 10705960 - Processors having virtually clustered cores and cache slices (2020-07-07),
2. 8782347 - Controllably exiting an unknown state of a cache coherency directory (2014-07-15),
3. 7930539 - Computer system resource access control (2011-04-19),
4. 7398374 - Multi-cluster processor for processing instructions of one or more instruction threads (2008-07-08),
5. 6941489 - Checkpointing of register file (2005-09-06),
6. 6931489 - Apparatus and methods for sharing cache among processors (2005-08-16),
7. 6895497 - Multidispatch CPU integrated circuit having virtualized and modular resources and adjustable dispatch priority (2005-05-17),
8. 6820167 - Configurable crossbar and related methods (2004-11-16),
9. 6427188 - Method and system for early tag accesses for lower-level caches in parallel with first-level cache (2002-07-30),
10. 5787494 - Software assisted hardware TLB miss handler (1998-07-28),
11. 5617549 - System and method for selecting and buffering even and odd instructions (1997-04-01),
12. 5526500 - System for operand bypassing to allow a one and one-half cycle cache (1996-06-11),
13. 5493660 - Software assisted hardware TLB miss handler (1996-02-20),
14. 5396604 - System and method for reducing the penalty associated with data cache (1995-03-07),

Title: The Inventive Journey of Eric R DeLano

Introduction: Eric R DeLano is a prolific inventor based in Fort Collins, Colorado, known for his groundbreaking contributions to various fields.

Latest Patents: Eric R DeLano holds several patents in the areas of technology, healthcare, and consumer products, showcasing his diverse range of innovative ideas.

Career Highlights: With a career spanning over two decades, Eric R DeLano has established himself as a visionary inventor with a keen eye for identifying gaps in the market and developing unique solutions.

Collaborations: Throughout his career, Eric R DeLano has collaborated with leading companies, research institutions, and universities to bring his inventions to life, demonstrating his ability to work effectively in multidisciplinary teams.

Conclusion: Eric R DeLano's passion for innovation and his relentless drive to push the boundaries of what is possible make him a standout figure in the world of inventors, with a legacy that continues to inspire future generations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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