Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Intel Corporation

Eric R DeLano

Samuel D Naffziger

Ganesh Kumar

Duncan C Weir

Michael A Buckley

Herbert H Hum

Dean A Mulla

Donald Charles Soltis, Jr

Eric J DeHaemer

James R Vash

Patrick Knebel

Leena K Puthiyedath

Brinda Ganesh

Rohit Bhatia

Adrian C Moga

Terry L Lyon

Eric S Fetzer

Richard Lawrence Carlson

Dheemanth Nagaraj

Wayne Kever

Gregory S Averill

David Bubien

Thomas R Hotchkiss

Scott J Erlanger

Michelle M Sebot

Mark A Forsyth

Vincent R Freytag

Darius F Tanksalvala

R Craig Simpson

A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Processors having virtually clustered cores and cache slices

In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message is sent to at least one other caching agent to invalidate information in a cache location of the other caching agent corresponding to the location of the read request, to enable setting of the directory entry into a known state. Other embodiments are described and claimed.

Controllably exiting an unknown state of a cache coherency directory

In a computer system including a plurality of resources, a device receives a request from a software program to access a specified one of the plurality of resources, determines whether the specified one of the plurality of resources is a protected resource. If the specified one of the plurality of resources is a protected resource, the device denies the request if the computer system is operating in a protected mode of operation, and processes the request based on access rights associated with the software program if the computer system is not operating in the protected mode of operation.

Computer system resource access control

The invention provides a processor that processes bundles of instructions preferentially through clusters or execution units according to thread characteristics. The cluster architectures of the invention preferably include capability to process 'multi-threaded' instructions. Selectively, the architecture either (a) processes singly-threaded instructions through a single cluster to avoid bypassing and to increase throughput, or (b) processes singly-threaded instructions through multiple processes to increase 'per thread' performance. The architecture may be &#x201c;configurable&#x201d; to operate in one of two modes: in a &#x201c;wide&#x201d; mode of operation, the processor's internal clusters collectively process bundled instructions of one thread of a program at the same time; in a &#x201c;throughput&#x201d; mode of operation, those clusters independently process instruction bundles of separate program threads. Clusters are often implemented on a common die, with a core and register file per cluster.

Multi-cluster processor for processing instructions of one or more instruction threads

The invention performs an extra read from a register of a register file prior to writing to that register. The data from the extra read is stored in a buffer (e.g., another register file). After a 'checkpoint' period, a check is made as to whether any data errors have occurred; if there are no errors, the buffer is flushed and processing continues per normal; if there are errors, the register file is rewritten with contents from the buffer and the program counter is reset to the prior checkpoint, wherein after processing re-executes program instructions from the last checkpoint. The checkpointing period may be defined by the memory size of the buffer; typically that buffer has a fraction of the memory capacity of the register file, since a flush occurs at every checkpoint. The register file of the invention may utilize an extra read port with the register file to perform the extra read. The extra read may occur for every write to the register file; alternatively, the extra read may occur for a subset of the writes to the register file.

Checkpointing of register file

A processing system including a plurality of processors, a cache data array, and a crossbar interface connecting the processors with the cache data array. Each processor includes a tag array mapped to the cache data array. In another embodiment, the cache data array includes a plurality of sub-arrays accessible via a plurality of ports of the crossbar interface. The system allows an upper-level cache data array to be shared among processors while cache latency is reduced.

Apparatus and methods for sharing cache among processors

A multiple dispatch processor has several instruction fetch units, each for providing a stream of instructions to an instruction decode and dispatch unit. The processor also has an resource allocation unit, and multiple resources such as combined integer and address execution pipelines and floating point execution pipelines. Each instruction decode and dispatch unit requests resources needed to perform an instruction of the resource allocation unit, which arbitrates among the multiple instruction decode and dispatch units.

Multidispatch CPU integrated circuit having virtualized and modular resources and adjustable dispatch priority

A processing system crossbar includes control sub-ports and mini-ports selectively configurable as connection points. Each control sub-port has a domain of mini-ports that the control sub-port is configured to selectively control. Each mini-port is configurable to select a control sub-port from those having domains that include the selecting mini-port. Each connection point includes a corresponding control sub-port and each mini-port selecting the corresponding control sub-port. The crossbar provides bandwidth tailored for various system agents. Thus crossbar bottlenecks are eliminated or reduced.

Configurable crossbar and related methods

A system and method are disclosed which determine in parallel for multiple levels of a multi-level cache whether any one of such multiple levels is capable of satisfying a memory access request. Tags for multiple levels of a multi-level cache are accessed in parallel to determine whether the address for a memory access request is contained within any of the multiple levels. For instance, in a preferred embodiment, the tags for the first level of cache and the tags for the second level of cache are accessed in parallel. Also, additional levels of cache tags up to N levels may be accessed in parallel with the first-level cache tags. Thus, by the end of the access of the first-level cache tags it is known whether a memory access request can be satisfied by the first-level, second-level, or any additional N-levels of cache that are accessed in parallel. Additionally, in a preferred embodiment, the multi-level cache is arranged such that the data array of a level of cache is accessed only if it is determined that such level of cache is capable of satisfying a received memory access request. Additionally, in a preferred embodiment the multi-level cache is partitioned into N ways of associativity, and only a single way of a data array is accessed to satisfy a memory access request, thereby preserving the remaining ways of a data array to save power and resources that may be accessed to satisfy other instructions.

Method and system for early tag accesses for lower-level caches in parallel with first-level cache

The present invention provides a software-assisted hardware TLB miss-handler which is designed to reduce the TLB miss penalty while being low cost to implement and requiring little chip area or complexity. When a TLB miss occurs, the HW TLB miss handler of the present invention computes a physical address of a page table entry located in a special hardware-visible table based on a missing virtual address. It accesses the page table entry and checks for a correct translation and status information. If correct, a physical page address and protection information of the page table entry are inserted into the TLB. The original virtual address is re-translated and normal program execution continues. If the correct translation and status are not found, the HW TLB miss-handler will not insert the entry and will trap to a more sophisticated SW TLB miss handler. A pointer to the page table entry is passed to the SW TLB miss handler so that the page table address need not be recomputed. Thus, the HW TLB miss-handler of the present invention services the simplest and most common TLB misses very quickly, reducing the overall TLB miss penalty. The slower SW TLB miss handler services the more complex and less common TLB misses and provides flexibility in the virtual memory management system.

Software assisted hardware TLB miss handler

The present invention is directed to a system and method for selecting instruction words from a memory system for simultaneous execution in an execution unit of a computer system. In one example, an instructor selector unit of the present invention employs an addressing unit to fetch instructions from an instruction cache. The instructor selector unit also employs a receiver unit for buffering and transferring multiple aligned as well as misaligned instructions. The instruction selector unit supplies these instructions to an instruction execution unit (having an integer unit and a floating point unit), which is capable of executing two bundled instructions simultaneously. The instruction selector unit can provide instructions to the instruction execution unit individually, or as a bundled pair.

System and method for selecting and buffering even and odd instructions

Pipeline structure that is arranged to allow 1.5 cycle access time for both data and instruction cache without imposing additional instruction step delays than that imposed by data and instruction cache that have 1 cycle access time. Half cycle pulses are produced to allow execution of various instructions in 0.5 cycles. A bypass signal is generated to allow data from a current load instruction to be available for a second subsequent instruction even though the access time for data cache is 1.5 cycles. Additionally, a branch address is available for a third subsequent instruction even though instruction cache access time is 1.5 cycles. The present invention shows the initiation of an instruction step for each cycle and 1.5 cycle access time for cache memory. The present invention can also be implemented by implementing an instruction every 2 cycles and providing 3 cycle access time for cache memory.

System for operand bypassing to allow a one and one-half cycle cache

A computer system having a central processor unit (CPU) with a reduced instruction set, a decoder and a data cache memory, for processing an instruction to retrieve data from a main memory to prevent a data cache miss. The system decodes an instruction requiring the CPU to load a value into a read only general purpose memory register, the instruction thereby indicating to the CPU to perform a prefetch operation and providing information corresponding to an address of the data to be fetched from the main memory. The system processes, substantially simultaneously, further instructions following the load register instruction and the prefetch operation by determining the address in main memory of the data to be prefetched using the information provided by the load instruction, fetching the data from the main memory, and storing the data in the data cache memory to permit accesses to the data and thereby reduce the penalty associated with a data cache miss.

Growing community of inventors

Fort Collins, CO, United States of America

Eric R DeLano