Los Altos, CA, United States of America

Era Kasturia Nangia

This inventor holds 12 USPTO granted patents. Top assignees: Arm Finance Overseas Limited, Mips Technologies, Inc., Mips Tech Limited. Active years: 2005-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Era Kasturia Nangia. Retrieved from https://idiyas.com/inventor/era-kasturia-nangia

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 83.3

Average Co-Inventor Count = 2.9

ph-index = 6

Forward Citations = 91(Granted Patents)


Company Filing History:


Years Active: 2005-2020

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12 patents (USPTO):Explore Patents

Title: Era Kasturia Nangia: Innovator in Processor Technology

Introduction

Era Kasturia Nangia is a prominent inventor based in Los Altos, California. He has made significant contributions to the field of processor technology, holding a total of 12 patents. His work focuses on enhancing the efficiency and performance of processors through innovative designs and methodologies.

Latest Patents

Among his latest patents is the "Load/store unit for a processor, and applications thereof." This invention features a load/store unit that includes a load/store queue designed to store information and data associated with a specific class of instructions. The data stored in the load/store queue can be bypassed to dependent instructions, ensuring efficient processing. Additionally, when an instruction associated with a cache miss graduates, control logic stores a pointer in a load/store graduation buffer, which points to an entry in the load/store queue. This mechanism guarantees that graduated instructions access shared resources in program order.

Another notable patent is the "Data cache virtual hint way prediction, and applications thereof." This invention introduces a virtual hint-based data cache way prediction scheme. In this embodiment, a processor retrieves data from a data cache using a virtual hint value or an alias way prediction value. The data is forwarded to dependent instructions before the physical address is available. Once the physical address is accessible, it is compared to a physical address tag value for the forwarded data to confirm its accuracy. If the data is correct, a hit signal is generated; otherwise, a miss signal is produced, leading to the invalidation or replay of any instructions that operated on incorrect data.

Career Highlights

Era has worked with notable companies such as Arm Finance Overseas Limited and MIPS Technologies, Inc. His experience in these organizations has allowed him to refine his skills and contribute to groundbreaking advancements in processor technology.

Collaborations

Throughout his career, Era has collaborated with talented individuals, including Meng-Bing Yu and Michael Ni. These partnerships have fostered innovation and have been instrumental in the development of his patented technologies.

Conclusion

Era Kasturia Nangia is a distinguished inventor whose work in processor technology has led to significant advancements in the field. His innovative patents and collaborations highlight his commitment to enhancing processor efficiency and performance.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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