Arm Finance Overseas Limited

Mips Technologies, Inc.

Mips Tech Limited

Era Kasturia Nangia

Meng-Bing Yu

Michael Ni

Lew Chua-Eoan

Vidya Rajagopalan

Ryan C Kinter

Karagada Ramarao Kishore

Ranjit Joseph Rozario

Ranganathan Sudhakar

Debasish Chandra

Alex Khainson

Donald C Ramsey, Jr

A load/store unit for a processor, and applications thereof. In an embodiment, the load/store unit includes a load/store queue configured to store information and data associated with a particular class of instructions. Data stored in the load/store queue can be bypassed to dependent instructions. When an instruction belonging to The particular class of instructions graduates and the instruction is associated with a cache miss, control logic causes a pointer to be stored in a load/store graduation buffer that points to an entry in the load/store queue associated with the instruction. The load/store graduation buffer ensures that graduated instructions access a shared resource of the load/store unit in program order.

Load/store unit for a processor, and applications thereof

A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.

Data cache virtual hint way prediction, and applications thereof

In one aspect, a processor has a register file, a private Level 1 (L1) cache, and an interface to a shared memory hierarchy (e.g., an Level 2 (L2) cache and so on). The processor has a Load Store Unit (LSU) that handles decoded load and store instructions. The processor may support out of order and multi-threaded execution. As store instructions arrive at the LSU for processing, the LSU determines whether a counter, from a set of counters, is allocated to a cache line affected by each store. If not, the LSU allocates a counter. If so, then the LSU updates the counter. Also, in response to a store instruction, affecting a cache line neighboring a cache line that has a counter that meets a criteria, the LSU characterizes that store instruction as one to be effected without obtaining ownership of the effected cache line, and provides that store to be serviced by an element of the shared memory hierarchy.

Processors and methods for cache sparing stores

A load/store unit for a processor, and applications thereof. In an embodiment, the load/store unit includes a load/store queue configured to store information and data associated with a particular class of instructions. Data stored in the load/store queue can be bypassed to dependent instructions. When an instruction belonging to the particular class of instructions graduates and the instruction is associated with a cache miss, control logic causes a pointer to be stored in a load/store graduation buffer that points to an entry in the load/store queue associated with the instruction. The load/store graduation buffer ensures that graduated instructions access a shared resource of the load/store unit in program order.

Livelocks are prevented in multiple core processors by canceling data access requests upon determining that they conflict with other data access requests. A requesting processor core sends a data access request potentially causing livelock to a cache coherency manager. A cache coherency manager receives data access requests from multiple processor. The cache coherency manager sends intervention messages to all of the processor cores in response to all data access requests that may cause livelock. Upon receiving an intervention message from the cache coherency manager, the processor core determines if the intervention message corresponds with any of its own pending data access requests. If the intervention message is associated with a data access request conflicting with one of its own pending data access requests, the processor core responds to the invention message by directing the cache coherency manager to cancel its own conflicting pending data access request.

Avoiding livelock using intervention messages in multiple core processors

A full-scan latch is provided that may be used to incorporate design for test functionality in an integrated circuit. The full-scan latch includes a shadow latch, a multiplexer, and a slave latch. The full-scan latch has a test mode and a normal mode. When in the normal mode, the device operates as a transparent latch, passing a data input to its output. When in test mode, the device is operable to pass scan data down a scan chain and to inject scan data into the data path.

Full scan solution for latched-based design

A method of designing a circuit includes annotating relative positions of instantiated hierarchical macro cells, which include two or more instantiated standard cells. The relative positions of individual instantiated standard cells may also be annotated. Relative positions of instantiated hierarchical macro cells and individual instantiated standard cells may be altered to form a more compact standard cell configuration. Pin positions may also be annotated by relative position. Relative pin positions may be altered to promote dense signal line routing within the standard cell design. The relative positions of the instantiated hierarchical macro cells and individual instantiated standard cells are converted to absolute grid position locations to form a grid assigned circuit. The grid assigned circuit is then routed.

Growing community of inventors

Los Altos, CA, United States of America

Era Kasturia Nangia