The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2005
Filed:
May. 31, 2002
Alex Khainson, Morgan Hill, CA (US);
Donald C. Ramsey, Jr., Los Altos Hills, CA (US);
Lew Chua-eoan, San Jose, CA (US);
Era K. Nangia, Los Altos, CA (US);
Alex Khainson, Morgan Hill, CA (US);
Donald C. Ramsey, Jr., Los Altos Hills, CA (US);
Lew Chua-Eoan, San Jose, CA (US);
Era K. Nangia, Los Altos, CA (US);
MIPS Technologies, Inc., Mountain View, CA (US);
Abstract
A method of designing a circuit includes annotating relative positions of instantiated hierarchical macro cells, which include two or more instantiated standard cells. The relative positions of individual instantiated standard cells may also be annotated. Relative positions of instantiated hierarchical macro cells and individual instantiated standard cells may be altered to form a more compact standard cell configuration. Pin positions may also be annotated by relative position. Relative pin positions may be altered to promote dense signal line routing within the standard cell design. The relative positions of the instantiated hierarchical macro cells and individual instantiated standard cells are converted to absolute grid position locations to form a grid assigned circuit. The grid assigned circuit is then routed.