Edward C Dasse

Title: Edward C. Dasse and Wafer-Level Integrated Circuit Testing.

Introduction

Edward C. Dasse is an inventor associated with Austin, Texas, and Motorola Corporation. His work includes innovations in testing integrated circuits directly at the wafer level. Dasse is credited with 4 patents.

Latest Patents

One of Dasse’s listed patents is titled “Apparatus for Performing Wafer-Level Testing of Integrated Circuits.” The invention divides a wafer’s integrated circuits into segmented bus regions, each with its own isolated set of test conductors. The conductors connect to contact pads positioned within the periphery of the integrated circuits’ active areas.

This segmented arrangement supports wafer-level testing of more high-powered integrated circuits while helping address challenges involving speed, power, throughput, and routing. The patent description also specifies that the contact pads are not placed over active circuitry, a design choice intended to improve yield.

Career Highlights

Dasse’s patent work reflects a focus on semiconductor testing and wafer-level test architecture. The described approach combines isolated test-conductor groups with carefully positioned contact pads to facilitate testing before individual chips are separated from the wafer.

Collaborations

Dasse’s listed coworkers include Charles F. Toewe and Thomas R. Yarbrough. His company affiliation is Motorola Corporation.

Conclusion

Edward C. Dasse’s patent work highlights a practical approach to wafer-level integrated circuit testing, using segmented bus regions and strategically placed contact pads to support testing efficiency and yield.