The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 1996

Filed:

Nov. 21, 1994
Applicant:
Inventors:

Edward C Dasse, Austin, TX (US);

Robert W Bollish, Austin, TX (US);

Alfredo Figueroa, Austin, TX (US);

James H Carlquist, Austin, TX (US);

Thomas R Yarbrough, Buda, TX (US);

Charles F Toewe, Austin, TX (US);

Kelvin L Holub, Austin, TX (US);

Marcus R Burton, Dripping Springs, TX (US);

Kenneth J Long, Austin, TX (US);

Walid S Ballouli, Austin, TX (US);

Assignee:

Motorola Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; G01R / ; G01R / ;
U.S. Cl.
CPC ...
257620 ; 257 48 ; 257734 ; 257536 ; 371 211 ; 371 225 ;
Abstract

A semiconductor wafer (20) having integrated circuit dice (22), wafer conductors (42-47, 50-53), and wafer contact pads (38) formed thereon. The wafer conductors (42-47, 50-53) are used to transfer electrical signals to and from the integrated circuit dice (22) on semiconductor wafer (20) so that wafer level testing and burn-in can be performed on the integrated circuit dice (22). In accordance with one embodiment of the present, each wafer conductor (45, 52) is electrically coupled to the same bonding pad (78) on each integrated circuit dice (22). Each wafer conductor (42-47, 50-53) includes at least a portion of conductor (42-47) which overlies the upper surface of at least one integrated circuit dice (22).


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