The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 1997
Filed:
Jun. 07, 1995
Edward C Dasse, Austin, TX (US);
Robert W Bollish, Austin, TX (US);
Alfredo Figueroa, Austin, TX (US);
James H Carlquist, Austin, TX (US);
Thomas R Yarbrough, Buda, TX (US);
Charles F Toewe, Austin, TX (US);
Kelvin L Holub, Austin, TX (US);
Marcus R Burton, Dripping Springs, TX (US);
Kenneth J Long, Austin, TX (US);
Walid S Ballouli, Austin, TX (US);
Shih King Cheng, Scottsdale, AZ (US);
Motorola Inc., Schaumburg, IL (US);
Abstract
Wafer level testing of a wafer (500) is accomplished by dividing the integrated circuits of the wafer into a plurality of segmented bus regions (514, 516, and 518 for example). Each bus region is formed having its own set of test conductors (520-530) wherein each set of test conductors are isolated from all other sets of test conductors on the wafer. Each test conductor has at least one contact pad (531-546) where each contact pad lies within a periphery of the integrated circuits' active areas. By forming pads over ICs and by sub-dividing the bus structure of test conductive lines, more high powered ICs can be tested in a wafer-level manner with fewer problems associated with speed, power, throughput, and routing problems.