Netanya, Israel

Dovev Amosi

This inventor holds 1 USPTO granted patent. Top assignee: Intel Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Dovev Amosi. Retrieved from https://idiyas.com/inventor/dovev-amosi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Dovev Amosi: Innovator in Chip Interconnect Technology

Introduction

Dovev Amosi is a notable inventor based in Netanya, Israel. He has made significant contributions to the field of chip interconnect technology. His innovative work focuses on enhancing the reliability and performance of interconnects between chips.

Latest Patents

Dovev Amosi holds a patent for a solution related to the test and repair of interconnects between chips. The patent describes a method that involves a first finite state machine (FSM) coupled to a set of transmit lanes on a chip. This method allows for the testing of each transmit lane individually by applying periodic signals and comparing detected signals to expected responses. This innovative approach aims to improve diagnostic capabilities for chip-to-chip interconnects.

Career Highlights

Dovev Amosi is currently employed at Intel Corporation, where he continues to work on cutting-edge technologies. His expertise in chip interconnects has positioned him as a valuable asset within the company. He has demonstrated a commitment to advancing the field through his inventive solutions.

Collaborations

Dovev collaborates with Adithya Kashyap, a fellow innovator at Intel Corporation. Together, they work on projects that aim to push the boundaries of technology in the semiconductor industry.

Conclusion

Dovev Amosi's contributions to chip interconnect technology exemplify the spirit of innovation. His patent and ongoing work at Intel Corporation highlight his dedication to improving the performance and reliability of semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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