The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2026
Filed:
Jul. 22, 2022
Intel Corporation, Santa Clara, CA (US);
Sreejit Chakravarty, San Jose, CA (US);
Adithya Kashyap, Mysuru, IN;
Vijaya Chelli, Daggubadu, IN;
Micha Shahar, Petah Tikva, IL;
Rakesh Kandula, Bangalore, IN;
Dovev Amosi, Natanya, IL;
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments herein relate to a test, repair, and diagnostic solution for chip-to-chip interconnects. In one aspect, on a first chip, a first finite state machine (FSM) is coupled to a set of transmit lanes. To test each transmit lane, one at a time, the first FSM is to apply a first periodic signal to a transmit lane under test and concurrently apply a second periodic signal to other transmit lanes of the set of transmit lanes, where a phase of the first periodic signal is opposite to a phase of the second periodic signal. A comparator compares a detected signal on the lane under test to an expected response. The comparator can be on the first chip, when the first chip is tested alone, or on a second chip, where the two chips are tested together.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile