Dilip K Bhavsar

Title: The Innovative Mind of Dilip K Bhavsar

Introduction

Dilip K Bhavsar is a notable inventor based in Shrewsbury, MA (US). He holds a total of 8 patents that showcase his contributions to technology and innovation. His work primarily focuses on advancements in memory systems and testing methodologies.

Latest Patents

One of his latest patents is titled "Apparatus and method for interfacing a high speed scan-path with slow-speed test equipment." This invention addresses the challenges of scan testing devices under test (DUT) that operate at different clock speeds than the test equipment. The system utilizes a scan-wheel formed by a plurality of scan-flops, allowing for efficient data shifting based on the DUT's clock speed. This innovation ensures that test data is accurately loaded and managed despite the differing clock rates.

Another significant patent is "Embedded RAM with self-test and self-repair with spare rows and columns." This self-repair method for random access memory (RAM) arrays involves writing and reading values to identify faulty memory cells. The process includes comparing addresses of newly discovered faulty cells with previously identified ones, ensuring efficient allocation of spare rows and columns for replacement. This invention enhances the reliability and longevity of RAM systems.

Career Highlights

Dilip K Bhavsar has worked with prominent companies such as Compaq Computer Corporation and Digital Equipment Corporation. His experience in these organizations has contributed to his expertise in the field of technology and innovation.

Collaborations

Throughout his career, Bhavsar has collaborated with notable individuals, including Donald A Priore and Tina P Zou. These collaborations have likely enriched his work and led to further advancements in his inventions.

Conclusion

Dilip K Bhavsar's contributions to technology through his patents reflect his innovative spirit and dedication to improving systems in the tech industry. His work continues to influence advancements in memory technology and testing methodologies.