Method for cost-effective production testing of input voltage levels of

Abstract

A boundary scan based VIH/VIL test scheme for a clock forwarded interface of an IEEE 1149.1 Standard-compliant electronic component is provided. The Standard-compliant component has a test access port (TAP) and a forwarded clock interface including data and forwarded clock inputs for receiving signals from and sending signals to external circuitry during a test operation. Connected to each of such component's data inputs is a clocked and an unclocked input buffer. Coupled to the TAP is an instruction register for receiving Standard defined and other test instructions provided by the external circuitry at the TAP. Also coupled to the TAP is a chain of boundary scan cells, each associated with a different one of the input pins and connected to the output of each input buffer coupled thereto, and a TAP controller for generating control signals to capture and shift data through the boundary scan cells in response to test instructions received by the instruction register. Compliance control circuitry, responsive to the instruction register and the TAP controller, operates to couple each BSR cell to the second input buffer when the instruction register has been loaded with a Standard defined instruction. When the instruction register has been loaded with an instruction corresponding to an input threshold voltage test of the data input pins, the compliance control circuitry couples the BSR cell to the first input buffer.