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For the Inventor, By the Inventor

San Jose, CA, United States of America

Dhawal Bavishi

LinkedIn
USPTO Granted Patents = 44 

 

Average Co-Inventor Count = 1.6

ph-index = 2

Forward Citations = 21(Granted Patents)


Company Filing History:

goldMedal43 out of 37,905 
 
Micron Technology Incorporated
 patents
where one patent can have more than one assignee

Years Active: 2020-2025

where 'Filed Patents' based on already Granted Patents

44 patents (USPTO):
1. 12346612 - Memory sub-system command fencing (2025-07-01),
2. 12236131 - Controller command scheduling in a memory system to increase command bus utilization (2025-02-25),
3. 12007917 - Priority scheduling in queues to access cache data in a memory sub-system (2024-06-11),
4. 12007898 - Utilizing a designated memory address to pre-fetch for memory sub-system with cache (2024-06-11),
5. 11983435 - Optimize information requests to a memory system (2024-05-14),
6. 11941291 - Memory sub-system command fencing (2024-03-26),
7. 11914520 - Separate read-only cache and write-read cache in a memory sub-system (2024-02-27),
8. 11847058 - Using a second content-addressable memory to manage memory burst accesses in memory sub-systems (2023-12-19),
9. 11809710 - Outstanding transaction monitoring for memory sub-systems (2023-11-07),
10. 11748273 - Secure data communication with memory sub-system (2023-09-05),
11. 11741008 - Disassociating memory units with a host system (2023-08-29),
12. 11740833 - Throttle response signals from a memory system (2023-08-29),
13. 11698756 - Cache-based memory read commands (2023-07-11),
14. 11675705 - Eviction of a cache line based on a modification of a sector of the cache line (2023-06-13),
15. 11669265 - Memory sub-system-bounded memory function (2023-06-06),

Title: **Innovative Mind: Dhawal Bavishi's Contributions to Memory Systems**

Introduction

Dhawal Bavishi, based in San Jose, California, is a prominent inventor known for his significant contributions to the field of memory systems. With a remarkable portfolio of 43 patents, Bavishi has developed innovative solutions that enhance data processing efficiency and resource management in memory subsystems.

Latest Patents

Among his latest patents, one focuses on "Controller command scheduling in a memory system to increase command bus utilization." This invention addresses the scheduling of commands on a command bus to optimize the usage of data bus resources. It provides a method to identify and schedule commands while preventing conflicts, ensuring efficient data handling.

Another notable patent is "Priority scheduling in queues to access cache data in a memory sub-system." This innovation entails a sophisticated mechanism where a processing device generates fill operations and determines the execution schedule based on assigned priority indicators for both fill and read operations. It showcases Bavishi's ability to streamline data access in memory architectures.

Career Highlights

Dhawal Bavishi is currently employed at Micron Technology Incorporated, where he has made significant strides in memory technology innovations. His expertise in command scheduling and priority management has positioned him as a key contributor to the company’s advancements in storage solutions.

Collaborations

Throughout his career, Dhawal has collaborated with talented individuals such as Trevor Conrad Meyerowitz and Laurent Isenegger. Working alongside these esteemed colleagues has further enhanced his ability to innovate and push the boundaries of technology in memory systems.

Conclusion

Dhawal Bavishi continues to be a vital figure in the realm of memory system innovations. His impressive patent record reflects a commitment to improving data processing and management efficiency. As technology evolves, Bavishi's work promises to play a crucial role in shaping the future of memory architecture.

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