Micron Technology Incorporated

Dhawal Bavishi

Trevor Conrad Meyerowitz

Laurent Isenegger

Robert Michael Walker

Patrick A La Fratta

Zhenlei Shen

Fangfang Zhu

Jeffrey Frederiksen

A method includes memory fencing in memory components of a memory sub-system and receiving a first number of commands and a second number of command for execution on a memory sub-system, receiving a memory fencing command associated with the first number of commands and the second number of commands, and executing at least one of the first number of commands before executing at least one of the second number of commands in response to receiving the memory fencing command. The method further includes executing the at least one of the first number of commands by moving data from a first location in the memory subsystem to a second location in the memory sub-system and executing the at least one of the second number of commands by reading data from the second location in the memory sub-system and sending the data to a host system.

Memory sub-system command fencing

A first command is scheduled on a command bus, where the first command requires use of a data bus resource at a first time period after scheduling the first command. Prior to the first time period, a second command is identified according to a scheduling policy. A determination is made whether scheduling the second command on the command bus will cause a conflict in usage of the at least one data bus resource. In response to determining that scheduling the second command will cause the conflict in usage, a third lower-priority command is identified for which scheduling on the command bus will not cause the conflict in usage. The third command is scheduled on the command bus prior to scheduling the second command, even though it has lower priority than the second command.

Controller command scheduling in a memory system to increase command bus utilization

A processing device in a memory sub-system generates a fill operation to store data from a memory device at a cache of a memory sub-system, assigns a first priority indicator to the fill operation associated with the data, and assigns a second priority indicator to a read operation associated with a request to read the data from the memory sub-system. The processing device further determines a schedule of executing the fill operation and the read operation based on the first priority indicator and the second priority indicator and executes the fill operation and the read operation based on the determined schedule.

Priority scheduling in queues to access cache data in a memory sub-system

Various embodiments described herein provide for a pre-fetch operation on a memory sub-system, which can help avoid a cache miss when the memory sub-system subsequently processes a read command from a host system.

Utilizing a designated memory address to pre-fetch for memory sub-system with cache

A system having a processing device and a controller, operatively connected to a memory sub-system via a communication channel, to: store information identifying an amount of available capacity of a buffer of the memory sub-system; transmit, through the communication channel to the memory sub-system, one or more write commands to store data in memory components of the memory sub-system, where the memory sub-system queues the one or more write commands in the buffer; update the information by deducting, from the amount of available capacity, an amount of buffer capacity used by the one or more write commands to generate a current amount of available capacity of the buffer; and determine whether to generate an information request to the memory sub-system based at least in part on the current amount of available capacity.

Optimize information requests to a memory system

A determination can be made of a type of memory access workload for an application. A determination can be made whether the memory access workload for the application is associated with sequential read operations. The data associated with the application can be stored at one of a cache of a first type or another cache of a second type based on the determination of whether the memory workload for the application is associated with sequential read operations.

Separate read-only cache and write-read cache in a memory sub-system

A request to access data at an address is received from a host system. A tag associated with the address is determined to not be found in first entries in a first content-addressable memory (CAM) or in second entries in a second CAM. Responsive to determining that the tag is not found in the first entries or in the second entries, a particular entry of the first entries that each includes valid data is selected. A determination is made whether the particular entry satisfies a condition indicating that content in the particular entry is to be stored in the second CAM. The content is associated with other data stored in the cache. Responsive to determining that the condition is satisfied, the content of the particular entry is stored in one of the second entries to maintain the data in the cache.

Using a second content-addressable memory to manage memory burst accesses in memory sub-systems

A system includes a first controller configured to adjust a count of a number of first transactions and adjust a count of a number of second transactions. The count of the number of first transactions and the count of the number of second transactions are adjusted when a first transaction or second transaction is either received or executed by a second controller. The second controller is coupled to the first controller and is configured to limit the number of first transactions to a particular quantity of outstanding first transactions, limit the number of second transactions to a particular quantity of outstanding second transactions, and limit a number of total transactions to a particular quantity of outstanding total transactions.

Outstanding transaction monitoring for memory sub-systems

Various embodiments described herein provide for secure data communication between a host system and a memory sub-system. For example, some embodiments use a salt value, symmetric encryption, and asymmetric encryption to facilitate secure data communication between the host system and the memory sub-system.

Secure data communication with memory sub-system

A command indicating a logical address and a length system is received from a host system. One or more memory units in a memory sub-system corresponding to the logical address and the length are identified. An indicator associated with the one or more memory units is set, to indicate that the one or more memory units are invalid. The one or more memory units are excluded from a media management operation performing in the memory sub-system.

Disassociating memory units with a host system

A memory system having memory components and a processing device to: receive, from a host system, write commands to store data in the memory components; store the write commands in a buffer; execute at least a portion of the write commands; determine an amount of available capacity of the buffer that becomes available after execution of at least the portion of the write commands; receive, from the host system, a request for information about available capacity of the buffer; and determine whether to transmit a response signal corresponding to the request based at least in part on the amount of available capacity.

Throttle response signals from a memory system

Various embodiments described herein provide for selectively sending a cache-based read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system.

Cache-based memory read commands

An indication to perform an eviction operation on a cache line in a cache can be received. A determination can be made as to whether at least one sector of the cache line is associated with invalid data. In response to determining that at least one sector of the cache line is associated with invalid data, a read operation can be performed to retrieve valid data associated with the at least one sector. The at least one sector of the cache line that is associated with the invalid data can be modified based on the valid data. Furthermore, the eviction operation can be performed on the cache line with the modified at least one sector.

Eviction of a cache line based on a modification of a sector of the cache line

Various embodiments described herein provide for execution of a memory function within a memory sub-system. For example, some embodiments provide for execution of certain memory-related functions internally within the memory sub-system, at the request of a host system, using one or more memory access operations (e.g., direct memory access operations) performed internally within the memory sub-system.

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San Jose, CA, United States of America

Dhawal Bavishi