Farmington, MN, United States of America

Dayanand K Reddy

This inventor holds 3 USPTO granted patents. Top assignee: Lsi Logic Corporation. Active years: 2001-2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Dayanand K Reddy. Retrieved from https://idiyas.com/inventor/dayanand-k-reddy

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.8

ph-index = 3

Forward Citations = 43(Granted Patents)


Location History:

  • Minneapolis, MN (US) (2001 - 2003)
  • Farmington, MN (US) (2006)

Company Filing History:


Years Active: 2001-2006

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3 patents (USPTO):Explore Patents

Title: Dayanand K Reddy: Innovator in Delay-Locked Loop Technology

Introduction

Dayanand K Reddy is a notable inventor based in Farmington, MN (US). He has made significant contributions to the field of electronics, particularly in the development of delay-locked loop (DLL) technologies. With a total of 3 patents to his name, Reddy has demonstrated his expertise and innovative spirit in his work.

Latest Patents

One of Reddy's latest patents is titled "Delay-locked loop with built-in self-test of phase margin." This invention provides a method and apparatus for measuring the phase margin of a DLL. In this system, a reference clock is applied to the reference input of the DLL, and an auxiliary variable delay is incorporated within the DLL. The variable delay is adjusted until the DLL becomes unstable, generating a phase margin output based on the value of the variable delay at which instability occurs.

Another significant patent is "System for measuring phase error between two clocks by using a plurality of phase latches with different respective delays." This invention features a phase error measurement circuit designed for integrated circuits. It includes first and second clock signal inputs, a phase lead detector, a phase lag detector, and a phase error measurement output. The phase lead detector utilizes a phase lead latch, while the phase lag detector employs a phase lag latch, both of which contribute to the overall phase error measurement output.

Career Highlights

Dayanand K Reddy is currently employed at LSI Logic Corporation, where he continues to innovate and develop advanced technologies. His work has had a significant impact on the field of electronics, particularly in the area of clock signal management and measurement.

Collaborations

Reddy has collaborated with several talented individuals throughout his career, including Ian MacPherson Flanagan and Joel J Christiansen. These collaborations have likely contributed to the success of his innovative projects and patents.

Conclusion

Dayanand K Reddy is a distinguished inventor whose work in delay-locked loop technology has advanced the field of electronics. His patents reflect his commitment to innovation and excellence in engineering.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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