The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2006
Filed:
Jun. 12, 2001
Applicants:
Ian M. Flanagan, Edina, MN (US);
Roger L. Roisen, Minnetrista, MN (US);
Dayanand K. Reddy, Farmington, MN (US);
Joel J. Christiansen, Independence, MN (US);
Inventors:
Ian M. Flanagan, Edina, MN (US);
Roger L. Roisen, Minnetrista, MN (US);
Dayanand K. Reddy, Farmington, MN (US);
Joel J. Christiansen, Independence, MN (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01); H04L 7/02 (2006.01); H03L 7/06 (2006.01); H03L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method and apparatus for measuring phase margin of a delay-locked loop (DLL) is provided in which a reference clock is applied to a reference input of the DLL. An auxiliary variable delay is coupled within the DLL and is varied until the DLL becomes unstable. A phase margin output is generated as a function of a value of the variable delay at which the DLL becomes unstable.