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For the Inventor, By the Inventor

Boise, ID, United States of America

David D Siek

USPTO Granted Patents = 13

Average Co-Inventor Count = 1.4

ph-index = 8

Forward Citations = 312(Granted Patents)


Location History:

  • Bosie, ID (US) (2003)
  • Boise, ID (US) (1999 - 2007)

Company Filing History:

goldMedal13 out of 38,002 
 
Micron Technology Incorporated
 patents

Years Active: 1999-2007

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13 patents (USPTO):Explore Patents
1. 7180802 - Method of stress-testing an isolation gate in a dynamic random access memory (2007-02-20),
2. 6999362 - Method of stress-testing an isolation gate in a dynamic random access memory (2006-02-14),
3. 6930503 - System for testing integrated circuit devices (2005-08-16),
4. 6870750 - DRAM array and computer system (2005-03-22),
5. 6756805 - System for testing integrated circuit devices (2004-06-29),
6. 6735132 - 6F2 DRAM array with apparatus for stress testing an isolation gate and method (2004-05-11),
7. 6590817 - 6F2 DRAM array with apparatus for stress testing an isolation gate and method (2003-07-08),
8. 6510533 - Method for detecting or repairing intercell defects in more than one array of a memory device (2003-01-21),
9. 6496027 - System for testing integrated circuit devices (2002-12-17),
10. 6167541 - Method for detecting or preparing intercell defects in more than one (2000-12-26),
11. 6066870 - Single digit line with cell contact interconnect (2000-05-23),
12. 5986955 - Method and apparatus for hiding data path equilibration time (1999-11-16),
13. 5866928 - Single digit line with cell contact interconnect (1999-02-02),

Title: David D Siek: Innovator in Dynamic Random Access Memory Technology

Introduction

David D Siek is a prominent inventor based in Boise, ID (US), known for his significant contributions to the field of dynamic random access memory (DRAM) technology. With a total of 13 patents to his name, Siek has made notable advancements that enhance the performance and reliability of memory systems.

Latest Patents

One of Siek's latest patents is titled "Method of stress-testing an isolation gate in a dynamic random access memory." This invention involves a DRAM array that includes a first memory cell, a second memory cell, and an isolation gate formed between them. The isolation gate is designed to provide electrical isolation between the two memory cells. The DRAM array also features a first switch with load electrodes and a control electrode that accepts a control signal. The first load electrode is connected to the isolation gate, while the second load electrode is grounded. Additionally, a second switch is included, which also has load electrodes and a control electrode for a second control signal, further enhancing the functionality of the DRAM system.

Career Highlights

David D Siek is currently employed at Micron Technology Incorporated, a leading company in semiconductor manufacturing. His work at Micron has allowed him to focus on innovative memory solutions that address the growing demands of modern computing.

Collaborations

Siek has collaborated with notable colleagues, including Joseph C Sher and Huy Thanh Vo, contributing to various projects that push the boundaries of memory technology.

Conclusion

David D Siek's contributions to dynamic random access memory technology through his patents and work at Micron Technology Incorporated highlight his role as a key innovator in the field. His inventions continue to influence the development of advanced memory systems, ensuring better performance and reliability in computing.

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