Method for detecting or preparing intercell defects in more than one

Abstract

A method of testing a memory device having two arrays of memory cells arranged in rows and columns. Sense amplifiers for respective columns are shared by the arrays, with the sense amplifiers being selectively coupled to the digit lines of respective columns in each array by respective isolation transistors. Cells of the memory array are tested by first writing known data bits to each of the cells. The isolation transistors for the first array are then turned on, and the isolation transistors for the second array are turned off. Predetermined voltages are coupled to the sense amplifiers through the digit lines of the first array by activating a row in the first array. A plurality of rows in the first array are then activated to couple the memory cells in each activated row to respective digit lines. The sense amplifiers are then coupled to respective digit lines in the second array by turning on the isolation transistors for the second array. A plurality of rows in the second array are then activated to couple the memory cells in each activated row to respective digit lines of the second array. The rows in the first and second arrays remain activated for a testing interval of sufficient duration to allow charge to transfer through any inter-cell defects between the cells in the activated rows and cells that are not in an activated row. The cells that are not in an activated row are then read to determine if the data originally written to the cells was altered by charge flowing through inter-cell defects. Inter-cell defects may also be repaired by activating the rows in the first and second arrays in a manner that couples adjacent memory cells to digit lines having different complimentary voltages.