Micron Technology Incorporated

David D Siek

Huy Thanh Vo

Hua Zheng

Joseph C Sher

Victor Wong

Nicholas Van Heel

Tim G Damon

Rajesh Somasekharan

The present invention includes a DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first and second memory cells. The DRAM also includes a first switch having first and second load electrodes and a control electrode configured to accept a first control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to ground. The DRAM additionally includes a second switch having first and second load electrodes and a control electrode configured to accept a second control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to a stress voltage source.

Method of stress-testing an isolation gate in a dynamic random access memory

A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

System for testing integrated circuit devices

DRAM array and computer system

A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

The present invention includes a 6F DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first and second memory cells. The DRAM also includes a first switch having first and second load electrodes and a control electrode configured to accept a first control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to ground. The DRAM additionally includes a second switch having first and second load electrodes and a control electrode configured to accept a second control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to a stress voltage source.

6F2 DRAM array with apparatus for stress testing an isolation gate and method

A method of testing and/or repairing a memory device having two arrays of memory cells arranged in rows and columns. Sense amplifiers shared by the arrays are selectively coupled by isolation transistors to the digit lines of respective columns in each array. The sense amplifiers and isolation transistors are controlled to sequentially writing known data bits to a plurality of rows in each of the arrays. The rows in the first and second arrays remain activated for a testing interval of sufficient duration to allow charge to transfer through any inter-cell defects between the cells in the activated rows and cells that are not in an activated row. Cells in each non-activated row are then read. Inter-cell defects may also be repaired by activating the rows in the first and second arrays in a manner that couples adjacent memory cells to digit lines having different complimentary voltages.

Method for detecting or repairing intercell defects in more than one array of a memory device

A method of testing a memory device having two arrays of memory cells arranged in rows and columns. Sense amplifiers for respective columns are shared by the arrays, with the sense amplifiers being selectively coupled to the digit lines of respective columns in each array by respective isolation transistors. Cells of the memory array are tested by first writing known data bits to each of the cells. The isolation transistors for the first array are then turned on, and the isolation transistors for the second array are turned off. Predetermined voltages are coupled to the sense amplifiers through the digit lines of the first array by activating a row in the first array. A plurality of rows in the first array are then activated to couple the memory cells in each activated row to respective digit lines. The sense amplifiers are then coupled to respective digit lines in the second array by turning on the isolation transistors for the second array. A plurality of rows in the second array are then activated to couple the memory cells in each activated row to respective digit lines of the second array. The rows in the first and second arrays remain activated for a testing interval of sufficient duration to allow charge to transfer through any inter-cell defects between the cells in the activated rows and cells that are not in an activated row. The cells that are not in an activated row are then read to determine if the data originally written to the cells was altered by charge flowing through inter-cell defects. Inter-cell defects may also be repaired by activating the rows in the first and second arrays in a manner that couples adjacent memory cells to digit lines having different complimentary voltages.

Method for detecting or preparing intercell defects in more than one

An integrated memory circuit comprises a plurality of memory cells and access transistors; and a digit line comprising conductive tabs extending from at least one side of a conductive digit line. The use of one digit line allows for a reduction in internal noise and coupling between digit line pairs. The use of one digit line also allows for a reduction in array size.

Single digit line with cell contact interconnect

A hidden data path minimizes equilibration delays in coupling differential data through a complementary data path. The hidden data path may be used for both reading and writing to the memory cell array. The hidden data path includes two sets of complementary I/O lines coupled in parallel between the memory cell array and the DC sense amplifier, and are alternatively coupled between the memory cell array and the DC sense amplifier to receive and transmit data. The set of complementary I/O lines not coupled is equilibrated during this time in preparation for coupling to and transmitting subsequent differential data. The hidden data path may also include two sets of data read lines coupled in parallel between the DC sense amplifier and the output circuitry if used for reading data from the memory cell array. Similarly, a second set of data write lines may be coupled in parallel between the input circuitry and write driver circuit when used for writing data to the memory cell array.

Growing community of inventors

Boise, ID, United States of America

David D Siek