This inventor holds 1 USPTO granted patent. Top assignee: Walsin Advanced Electronics Ltd.. Active years: 2003.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2003
Title: Cs Yang and Wafer-Level Chip-Size Packaging
Introduction
Cs Yang is an inventor associated with Kaohsiung, Taiwan. His patent work concerns wafer-level chip-size packaging, a manufacturing approach designed to create electrical connections within a compact package.
Latest Patents
The provided information lists one patent for Yang: “Method for Manufacturing Wafer Level Chip Size Package.” The method secures a wafer to a partly etched lead frame, packages the lead frame, and then drills a blind hole that is filled with conductive material. This creates an electrical connection between the lead frame and the wafer after packaging. Yang is credited with 1 patent.
Career Highlights
Yang is associated with Walsin Advanced Electronics Ltd. His listed invention addresses a packaging process that integrates electrical connections into a wafer-level chip-size package.
Collaborations
The provided information names Chang Chao-Chia and Spencer Su as Yang’s coworkers. Their specific roles in the patent or related work are not stated.
Conclusion
Cs Yang’s listed patent focuses on a manufacturing method for establishing electrical connections in wafer-level chip-size packages, reflecting his work in semiconductor packaging innovation.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile