Hsinchu, Taiwan

Chung-Lun Hong

This inventor holds 1 USPTO granted patent. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., TSMC China Company Limited. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chung-Lun Hong. Retrieved from https://idiyas.com/inventor/chung-lun-hong

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Chung-Lun Hong: Semiconductor Testing and ESD Detection

Introduction

Chung-Lun Hong is an inventor associated with Hsinchu, Taiwan. His patent work concerns semiconductor-device testing, with a focus on detecting electrostatic-discharge damage to metal-oxide-semiconductor transistors.

Latest Patents

Hong is associated with 1 patent: “Resistive-Network Cell Region, Built-In Self-Tester Including Same, Semiconductor Device Including Same, Method of Operating Same and Method of Manufacturing Same.” The invention describes a built-in self-tester that uses an input/output circuit and one or more resistive-network cell regions to affect a reference current at an I/O terminal. A switching arrangement connects the regions to different reference voltages in separate phases, and the tester uses the phase and the input-buffer output signal to determine whether MOS transistors have sustained ESD damage.

Career Highlights

Hong’s listed company affiliations include Taiwan Semiconductor Manufacturing Company Limited and TSMC China Company Limited. These affiliations place his work in the semiconductor manufacturing sector, where reliable device testing is important.

Collaborations

The patent describes a testing approach involving semiconductor-device circuitry and resistive-network cell regions. The available information does not identify additional co-inventors or collaborators.

Conclusion

Chung-Lun Hong’s patent focuses on built-in semiconductor testing that can help identify ESD damage through phased reference-voltage measurements.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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