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For the Inventor, By the Inventor

Allen, TX, United States of America

Chris Michael Brueggen

This inventor holds 17 USPTO granted patents and 1 published patent application, primarily in Memory Management. Top assignees: Hewlett Packard Enterprise Development LP, Hewlett-Packard Development Company, L.p.. Active years: 2007-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chris Michael Brueggen. Retrieved from https://idiyas.com/inventor/chris-michael-brueggen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 17 

% Patents Active = 88.2

Average Co-Inventor Count = 1.6

ph-index = 2

Forward Citations = 64(Granted Patents)


Location History:

  • Dallas, TX (US) (2007)
  • Richardson, TX (US) (2010)
  • Plano, TX (US) (2018 - 2019)
  • Allen, TX (US) (2011 - 2021)

Company Filing History:

goldMedal11 out of 5,697 
 
Hewlett Packard Enterprise Development LP
 patents
silverMedal6 out of 27,691 
 
Hewlett-Packard Development Company, L.p.
 patents

Years Active: 2007-2021

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Areas of Expertise:
Byte-Addressable Memory
Data Corruption Prevention
Error Correction Codes
Fault-Tolerant Memory
List Decode Circuits
Memory Controller
Cache Line Management
Resource Arbitration
Priority Selection Circuit
Data Partitioning
Node Controllers
Memory Device Management
17 patents (USPTO):Explore Patents
1. 10922178 - Masterless raid for byte-addressable non-volatile memory (2021-02-16),
2. 10735030 - Re-encoding data associated with failed memory devices (2020-08-04),
3. 10666294 - Error correction code words with binomial bit error distribution (2020-05-26),
4. 10567003 - List decode circuits (2020-02-18),
5. 10402287 - Preventing data corruption and single point of failure in a fault-tolerant memory (2019-09-03),
6. 10367529 - List decode circuits (2019-07-30),
7. 10312943 - Error correction code in memory (2019-06-04),
8. 10275307 - Detection of error patterns in memory dies (2019-04-30),
9. 10243587 - Managing results from list decode methods (2019-03-26),
10. 10176043 - Memory controller (2019-01-08),
11. 10050641 - List manipulation circuits (2018-08-14),
12. 8521940 - Paired node controllers (2013-08-27),
13. 8370582 - Merging subsequent updates to a memory location (2013-02-05),
14. 8316189 - Rescinding ownership of a cache line in a computer system (2012-11-20),
15. 8085801 - Resource arbitration (2011-12-27),

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Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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