Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Chris Michael Brueggen

Gregg Bernard Lesartre

Martin Foltin

Harvey Ray

Craig William Warner

Derek Alan Sherlock

Russ William Herrell

Lidia Warnes

Kevin L Miller

Ron Roth

Theodore Carter Briggs

Jay Tsao

Brian S Birk

Cesar Garzon

Jonathan George

A system includes byte-addressable non-volatile memory (NVM) modules. The system includes media controllers communicatively connected to one another over a memory semantic fabric. Each media controller is responsible for a corresponding NVM module to which the media controller is attached. The media controllers cooperatively provide redundant array of independent disks (RAID) functionality at a granularity at which the NVM modules are byte-addressable without employing a master RAID controller.

Masterless raid for byte-addressable non-volatile memory

A technique includes determining that a given memory device of a plurality of memory devices has failed and in response to the determination that the given memory device has failed, re-encoding a data unit associated with the given memory device. The data unit is associated with a payload and a symbol-based error correction code. The re-encoding includes determining a bit-based error correction code for the payload and replacing the data unit in the memory with the payload and the bit-based error correction code.

Re-encoding data associated with failed memory devices

An error injected error correction code (ECC) word generator generates a set of ECC code words injected with bit errors for being read by an ECC decoder and error reporting hardware. The set of the error injected ECC words has a binomial distribution with regard to a number of the bit errors in a given ECC word of the set. The set of error injected ECC words has a predetermined average ratio of bit errors.

Error correction code words with binomial bit error distribution

Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a list decode circuit may include a syndrome calculation circuit, a symbol erasure circuit, an erasure syndrome calculation circuit and a Berlekamp-Massey algorithm circuit (BMA), and an error locator polynomial (ELP) evaluation circuit. The syndrome calculation circuit may calculate a baseline syndrome and erasure syndrome calculation circuit may calculate erasure syndromes from error locator polynomials calculated by the symbol erasure circuit. The BMA circuit may use the calculated syndromes to generate a series of ELPs, which may be used by the ELP evaluation circuit to identify error locations in a codeword.

List decode circuits

According to an example, data corruption and single point of failure is prevented in a fault-tolerant memory fabric with multiple redundancy controllers by granting, by a parity media controller, a lock of a stripe to a redundancy controller to perform a sequence on the stripe. The lock may be broken in response to determining a failure of the redundancy controller prior to completing the sequence. In response to breaking the lock, the parity cacheline of the stripe may be flagged as invalid. Also, a journal may be updated to document the breaking of the lock.

Preventing data corruption and single point of failure in a fault-tolerant memory

Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a device may include a first and second polynomial evaluation circuit, a field division circuit, a discrepancy filter, and an enhanced error locator polynomial (ELP) circuit. The first and second polynomial evaluation circuits may respectively evaluate a first and second polynomial output from a Berlekamp-Massey algorithm over a plurality of values in a finite field. The field division circuit may divide the outputs from the evaluations to generate a plurality of speculative discrepancy values for an additional iteration of the Berlekamp-Massey algorithm. The discrepancy filter circuit may filter the speculative discrepancy values down to a list of potentially valid discrepancy values that may be used by the enhanced ELP circuit to generate an enhanced ELP.

In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.

Error correction code in memory

A method is provided. In an example, the method includes identifying a memory module that includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a plurality of memory regions, and each memory die of the plurality of memory dies services a respective portion of a data access. An error pattern is detected in a first memory region of the plurality of memory regions. The first memory region is associated with a first memory die of the plurality of memory dies. Based on the detected error pattern, the first memory region of the first memory die is marked as erased without marking a second memory region of the first memory die as erased.

Detection of error patterns in memory dies

Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of circuits for managing results from list decode methods. In accordance with some examples disclosed herein, a plurality of potential error patterns for correcting errors in a codeword may be received. The plurality of potential error patterns may be generated using a plurality of different list decode methods. Error patterns among the plurality of potential error patterns may be determined and marked as candidate error patterns using a set of error pattern screens. Error weights may be assigned to the candidate error patterns based on a quantity of bit errors in each symbol included therein. Weights for candidate error patterns that are indicative of a memory device failure may be adjusted using a scaling factor. An error pattern among the candidate error patterns may be selected to correct the errors in the codeword based on the assigned error weights.

Managing results from list decode methods

Example implementations relate to a memory controller. For example, an apparatus includes a data storage device and a memory controller coupled to the data storage device. The memory controller is to perform, during a memory scrubbing operation, a corrective action to correct an error associated with a data block stored in the data storage device. The memory control is to determine, during the memory scrubbing operation, whether the corrective action is successful. In response to a determination that the corrective action is a failed corrective action, the memory controller is to fix a hardware failure of the data storage device based on a type of the hardware failure.

Memory controller

Examples disclosed herein relate to very large-scale integration (VLSI) list manipulation circuits. In accordance with some examples disclosed herein, a list manipulation circuit may include a progressive population count circuit to generate population count values. The population count values may be fed into various types of circuits, such as list conversion circuits, list compactor circuits, and list reordering circuits.

List manipulation circuits

In at least some embodiments, an apparatus comprises a pair of node controllers, each of the node controllers having a different processor assigned thereto. Each node controller is operable to selectively switch processor requests received from its assigned processor to the other node controller and to selectively switch responses to the processor requests to the other node controller.

Paired node controllers

A method of merging subsequent updates to a memory location includes receiving, at a first stage in an update pipeline, a first request to update a status word at a first address of a cache memory and receiving the status word from the cache memory. The method continues with determining, at a stage subsequent to the first stage, that a second request to update the status word has been received. Further included is updating the status word according to the first and second requests to form an updated status word and writing the updated status word to the cache memory.

Merging subsequent updates to a memory location

A method of rescinding ownership of a cache line in a computer system includes constructing a table of caching agent representations in which each caching agent representation is accompanied by a validity indicator. The method continues with receiving a cache line sharing list, with each entry of the cache line sharing list indicating the potential ownership of the cache line by one or more caching agent representations that correspond to an entry of the sharing list. The method also includes conveying a snoop packet to a caching agent when the logical conjunction of an entry of the cache line sharing list that corresponds to a caching agent representation and the accompanying validity indicator meets a predetermined Boolean condition.

Rescinding ownership of a cache line in a computer system

A circuit includes queue buffers, a bid masking circuit, and a priority selection circuit. Each of the queue buffers carries packets of a respective message class selected from a set of message classes and asserts a respective bid signal indicating that the queue buffer carries a packet that is available for transmission. The bid masking circuit produces a masked vector of bid signals by selectively masking one or more of the bid signals asserted by the queue buffers based on credit available to transmit the packets and on cyclical masking of one or more of the bid signals asserted by ones of the queue buffers selected for packet transmission. The priority selection circuit selects respective ones of the queue buffers from which packets are transmitted based on the masked vector of bid signals produced by the bid masking circuit.

Growing community of inventors

Allen, TX, United States of America

Chris Michael Brueggen