This inventor holds 2 USPTO granted patents. Top assignee: Chartered Semiconductor Manufacturing Ltd (Corporation). Active years: 2006-2007.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2006-2007
Title: Chok Kho Liep: Innovator in Semiconductor Technology
Introduction
Chok Kho Liep is a notable inventor based in Singapore, recognized for his contributions to semiconductor technology. He holds 2 patents that showcase his innovative approach to improving bond pad structures in semiconductor devices. His work has significantly impacted the efficiency and reliability of electronic components.
Latest Patents
Chok Kho Liep's latest patents focus on a structure and method for fabricating an improved bond pad structure. This invention involves a top wiring layer and a top dielectric (IMD) layer over a semiconductor structure. The process includes forming a buffer dielectric layer over these components, creating a buffer opening that exposes part of the top wiring layer. A barrier layer is then applied, followed by a conductive buffer layer that is planarized to create a buffer pad. A passivation layer is formed over the buffer pad, leading to the creation of a bond pad opening. Finally, a bond pad support layer and a bond pad layer are patterned to complete the bond pad structure.
Career Highlights
Chok Kho Liep is currently employed at Chartered Semiconductor Manufacturing Ltd, where he continues to develop innovative solutions in semiconductor fabrication. His expertise in this field has made him a valuable asset to his organization.
Collaborations
Chok Kho Liep has collaborated with notable colleagues such as Zhang Fan and Liu Wuping, contributing to advancements in semiconductor technology through teamwork and shared expertise.
Conclusion
Chok Kho Liep's work in semiconductor technology exemplifies innovation and dedication to improving electronic components. His patents reflect a commitment to enhancing the efficiency and reliability of semiconductor devices.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile