Taipei Hsien, Taiwan

Ching Lu Hsu


Average Co-Inventor Count = 3.2

ph-index = 2

Forward Citations = 5(Granted Patents)


Location History:

  • Taipei Hsien, JP (2003)
  • Taipei Hsien, TW (2005)
  • Zhubei, TW (2023)
  • Hsinchu County, TW (2023 - 2024)

Company Filing History:


Years Active: 2003-2025

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7 patents (USPTO):Explore Patents

Title: Ching Lu Hsu: Innovator in Integrated Circuit Design

Introduction

Ching Lu Hsu is a prominent inventor based in Taipei Hsien, Taiwan. He has made significant contributions to the field of integrated circuit design, holding a total of seven patents. His innovative methods focus on optimizing design rule checks and improving the efficiency of electronic circuit layouts.

Latest Patents

One of Hsu's latest patents is titled "Post-routing congestion optimization." This method involves identifying design rule check (DRC) violations in integrated circuit layouts and relocating target cells to minimize resource costs. Another notable patent is "Hard-to-fix (HTF) design rule check (DRC) violations prediction." This method utilizes machine learning to predict fix rates of DRC violations and identifies hard-to-fix issues, streamlining the correction process through an engineering change order tool.

Career Highlights

Hsu has worked with leading companies in the semiconductor industry, including Taiwan Semiconductor Manufacturing Company Ltd. and General Semiconductor Taiwan Ltd. His experience in these organizations has allowed him to refine his skills and contribute to groundbreaking advancements in circuit design.

Collaborations

Throughout his career, Hsu has collaborated with talented individuals such as Yi-Lin Chuang and Shih-Yao Lin. These partnerships have fostered a creative environment that has led to innovative solutions in the field of integrated circuits.

Conclusion

Ching Lu Hsu's work in integrated circuit design exemplifies the impact of innovation in technology. His patents and collaborations highlight his commitment to advancing the field and addressing complex challenges in electronic circuit layouts.

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