The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2005

Filed:

May. 30, 2003
Applicants:

Max Chen, Taipei Hsien, TW;

Ching LU Hsu, Taipei Hsien, TW;

Kuang Hann Lin, Taipei, TW;

Yan-man Tsui, Union City, CA (US);

Inventors:

Max Chen, Taipei Hsien, TW;

Ching Lu Hsu, Taipei Hsien, TW;

Kuang Hann Lin, Taipei, TW;

Yan-Man Tsui, Union City, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/44 ; H01L021/48 ; H01L021/50 ;
U.S. Cl.
CPC ...
Abstract

The present invention provides a semiconductor device packaging assembly and method for manufacturing the assembly. Preferably, the method of the present invention is used to assemble a plurality of semiconductor chips, such that the throughput of assembly can be enhanced. The method comprises the steps of: providing a bottom frame matrix including a plurality of bottom frame units, each of which unit comprises a bottom supporting portion and a bottom frame portion; providing a bridge frame including a plurality of bridge frame units, each of which unit comprises a bridge frame portion and a plurality of conducting bars; placing each of the semiconductor chips on each of the bottom supporting portions, respectively; and bonding each bottom frame unit and each bridge frame unit together, wherein, the conducting bars extending from each bridge frame portion toward corresponding chips are electrically coupled to bonding areas of the corresponding chips.


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