Taiwan Semiconductor Manufacturing Comp. Ltd.

General Semiconductor of Taiwan, Ltd.

General Semiconductor Taiwan, Ltd.

Ching Lu Hsu

Yi-Lin Chuang

Shih-Yao Lin

Max Sk Chen

Kuang Hann Lin

Heng-Yi Lin

Yan-Man Tsui

A method includes: identifying a first design rule check (DRC) violation in a cluster box on an integrated circuit layout; locating a first target cell at a first original location in the cluster box, the first target cell being connected to the first DRC violation; detecting a first plurality of candidate locations for the first target cell in the cluster box; calculating resource costs associated with the first plurality of candidate locations; determining a first relocation location, among the first plurality of candidate locations, associated with a minimum resource cost for the first target cell; and relocating the first target cell from the first original location to the first relocation location.

Post-routing congestion optimization

A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and fixing, by an engineering change order (ECO) tool, the DRC violations.

Hard-to-fix (HTF) design rule check (DRC) violations prediction

The present invention provides a semiconductor device packaging assembly and method for manufacturing the assembly. Preferably, the method of the present invention is used to assemble a plurality of semiconductor chips, such that the throughput of assembly can be enhanced. The method comprises the steps of: providing a bottom frame matrix including a plurality of bottom frame units, each of which unit comprises a bottom supporting portion and a bottom frame portion; providing a bridge frame including a plurality of bridge frame units, each of which unit comprises a bridge frame portion and a plurality of conducting bars; placing each of the semiconductor chips on each of the bottom supporting portions, respectively; and bonding each bottom frame unit and each bridge frame unit together, wherein, the conducting bars extending from each bridge frame portion toward corresponding chips are electrically coupled to bonding areas of the corresponding chips.

Method for assembling a semiconductor chip utilizing conducting bars rather than bonding wires

The present invention provides a semiconductor device packaging assembly and method for manufacturing the assembly. Preferably, the method of the present invention is used to assemble a plurality of semiconductor chips, such that the throughput of assembly can be enhanced, by providing a bottom frame matrix including a plurality of bottom frame units, each of which unit includes a bottom supporting portion and a bottom frame portion; providing a bridge frame including a plurality of bridge frame units, each of which unit includes a bridge frame portion and a plurality of conducting bars; placing each of the semiconductor chips on each of the bottom supporting portions, respectively; and bonding each bottom frame unit and each bridge frame unit together, wherein, the conducting bars extending from each bridge frame portion toward corresponding chips are electrically coupled to bonding areas of the corresponding chips.

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Taipei Hsien, Taiwan

Ching Lu Hsu