Chin Ta Su

Title: Chin Ta Su: Semiconductor Process and Wafer-Protection Innovations.

Introduction

Chin Ta Su is an inventor based in Erlun Shiang, Taiwan. His work includes semiconductor manufacturing technologies, and he is associated with Macronix International Co., Ltd. Su is credited with 5 patents.

Latest Patents

Among Su’s latest patents is “Chemical Mechanical Planarization Process and Structures.” The invention describes a semiconductor device with a substrate divided into first and second regions. A structure is formed over each region, and the structures have different heights.

Another patent, “System and Method for Semiconductor Wafer Processing with Side/Bevel Protection,” concerns protecting a wafer’s circumferential side during processing. The system applies a polymer coating to the wafer’s side using electrophoresis before electroplating a damascene layer. The coating acts as a barrier against damascene-layer formation on the side while leaving at least portions of the wafer’s front and back surfaces uncoated.

Career Highlights

Su’s patent work addresses practical challenges in semiconductor fabrication, including planarization structures and wafer-edge protection during electroplating. These inventions reflect a focus on process control and protecting wafer surfaces during manufacturing.

Collaborations

Su’s listed coworkers include Yung Tai Hung and Lee Chen. His work is associated with Macronix International Co., Ltd.

Conclusion

Chin Ta Su’s patents highlight contributions to semiconductor processing, particularly in chemical mechanical planarization and wafer-side protection.