Lawrenceville, NJ, United States of America

Chih-Jen Lin

This inventor holds 4 USPTO granted patents. Top assignees: Agere Systems Inc., At&t Bell Laboratories, At+t Corp.. Active years: 1994-2001.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chih-Jen Lin. Retrieved from https://idiyas.com/inventor/chih-jen-lin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 1.5

ph-index = 3

Forward Citations = 142(Granted Patents)


Location History:

  • Lawrenceville, NJ (US) (1994 - 1998)
  • Portland, OR (US) (2001)

Company Filing History:


Years Active: 1994-2001

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4 patents (USPTO):Explore Patents

Title: Innovations of Chih-Jen Lin

Introduction

Chih-Jen Lin is a notable inventor based in Lawrenceville, NJ (US). He has made significant contributions to the field of engineering, particularly in the area of built-in self-test (BIST) methodologies. With a total of 4 patents to his name, Lin's work has advanced the efficiency and effectiveness of testing circuits.

Latest Patents

One of Lin's latest patents is titled "Hybrid algorithm for test point selection for scan-based BIST." This innovative method calculates a hybrid cost reduction (HCR) value, which serves as an estimated value of the actual cost reduction for all nodes in a circuit under test. The process involves selecting a test point with the largest HCR and continues iteratively until the desired fault coverage is achieved or the maximum number of test points is reached. Additionally, in an alternative embodiment, the cost reduction factor is calculated for all nodes, while the HCR is determined for a selected set of candidates. This method not only enhances fault coverage results but also reduces computational processing compared to conventional selection methods.

Another significant patent is the "Method for inserting test points for full-and-partial-scan built-in." This patent describes a technique for placing test points at selected nodes within a circuit based on a cost function. The cost function considers both the global improvement in testability and the performance penalties associated with propagation delays due to the test points. By balancing these factors, the method maximizes fault coverage while minimizing circuit performance impairment.

Career Highlights

Chih-Jen Lin has worked with prominent companies such as AT&T Corp. and Agere Systems Inc. His experience in these organizations has allowed him to apply his innovative ideas in practical settings, contributing to advancements in circuit testing technologies.

Collaborations

Lin has collaborated with esteemed colleagues, including Kwang-Ting Cheng and Sudipta Bhawmik. These partnerships have fostered a collaborative environment that encourages the exchange of ideas and further innovation in the field.

Conclusion

Chih-Jen Lin's contributions to the field of engineering through his patents and collaborations have significantly impacted the efficiency of circuit testing methodologies. His innovative approaches continue to influence the industry and pave the way for future advancements.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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