Partial-scan built-in self-test technique

Abstract

Testing of an integrated circuit (10), configured of a plurality of flip-flops (14.sub.1 -14.sub.n), at least a portion of which are arranged in a scan chain (16.sub.1 -16.sub.k), is carried out by replacing each self-looping, non-scan chain flip-flop (14.sub.6) with an initializable non-scan flip-flop (64). The integrated circuit (10), including each initializable flip-flop (64) therein, is then initialized prior to placing the integrated circuit in a non-operational mode. During the non-operational mode, a first test vector is shifted through the scan chain flip-flops, causing each to shift out a bit previously latched therein. The integrated circuit (10) is then returned to an operational mode, after which time, a second test vector is applied to its inputs, causing a response to appear at its outputs, and also causing a bit to be shifted into each scan chain flip-flop. The response of the integrated circuit is compacted with the bits shifted from the scan chain flip-flops. By repeating this process for a predetermined number of cycles, a very high indication of the faults in the circuit can be had.