This inventor holds 1 USPTO granted patent. Top assignee: Globalwafers Co., Ltd.. Active years: 2026.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2026
Title: Chien Hung Chen and Wafer Grinding Optimization.
Introduction
Chien Hung Chen is an inventor associated with Hsinchu, Taiwan. His patent work focuses on optimizing wafer grinding parameters for semiconductor processing equipment.
Latest Patents
Chen is credited with 1 patent: “Wafer Grinding Parameter Optimization Method and Electronic Device.” The method obtains the natural frequency of a wafer-processing grinding wheel spindle and uses it to generate a grinding stability lobe diagram. It selects a grinding speed within the spindle’s speed range, evaluates multiple grinding parameter combinations through simulations, and chooses a specific combination based on the simulation results. The equipment can then be configured using the selected parameters.
Career Highlights
Chen is associated with GlobalWafers Co., Ltd. His patent describes a simulation-based approach to selecting grinding parameters, with the aim of supporting stable wafer processing.
Collaborations
The provided information identifies Chih-Chun Cheng and Wen-Nan Cheng as Chen’s coworkers. It does not specify their roles in the patent or whether they collaborated on it.
Conclusion
Chien Hung Chen’s patent presents a structured method for optimizing wafer grinding through spindle-frequency analysis and simulation, connecting his work in Hsinchu with semiconductor manufacturing at GlobalWafers Co., Ltd.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile