Tainan, Taiwan

Chieh-Ning Yang

This inventor holds 1 USPTO granted patent and 2 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chieh-Ning Yang. Retrieved from https://idiyas.com/inventor/chieh-ning-yang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Chieh-Ning Yang: Semiconductor Device Inventor

Introduction

Chieh-Ning Yang is an inventor associated with Tainan, Taiwan. His work includes a patent for a semiconductor device structure and methods of forming it. Yang is associated with Taiwan Semiconductor Manufacturing Company, Ltd.

Latest Patents

Yang is credited with 1 patent: “Semiconductor Device Structure and Methods of Forming the Same.” The invention describes a structure with a first gate structure over a substrate in an active device region and insulating material in a passive device region. A resistor structure sits over the insulating material, with a first conductive contact electrically connected to the resistor and a second conductive contact positioned above it. A dielectric layer contacts both the second conductive contact and the resistor structure.

Career Highlights

Yang’s patent addresses the design and formation of semiconductor device structures that combine active and passive device regions. The disclosed arrangement includes a resistor and conductive contacts integrated with the substrate structure.

Collaborations

Yang is identified as a coworker of Nai-Hsin Ting. Both are associated with Taiwan Semiconductor Manufacturing Company, Ltd.

Conclusion

Chieh-Ning Yang’s recorded patent focuses on a semiconductor structure that integrates a resistor, conductive contacts, and dielectric material within a device containing active and passive regions.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…